Abstract
Micro-Controller Units (MCUs) are widely adopted ubiquitous computing devices. Due to tight cost and energy constraints, MCUs often integrate very limited internal RAM memory on top of Flash storage, which exposes Flash to heavy write traffic and results in short system lifetime. Architecting emerging Phase Change Memory (PCM) is a promising approach for MCUs due to its fast read speed and long write endurance.
However, PCM, especially multi-level cell (MLC) PCM, has long write latency and requires large write energy, which diminishes the benefits of its replacement of traditional Flash. By studying MLC PCM write operations, we observe that writing MLC PCM can take advantages of two write modes --- fast write leaves cells in volatile state, and slow write leaves cells in non-volatile state. In this paper, we propose a compiler directed dual-write (CDDW) scheme that selects the best write mode for each write operation to maximize the overall performance and energy efficiency. Our experimental results show that CDDW reduces dynamic energy by 32.4%(33.8%) and improves performance by 6.3%(35.9%) compared with an all fast(slow) write approach.
- AbsInt. ait worst-case execution time analyzers, 2013. URL http://www.absint.com/ait/index.htm.Google Scholar
- A. V. Aho, R. Sethi, and J. D. Ullman. phCompilers: principles, techniques, and tools. Addison-Wesley Longman Publishing Co., Inc., Boston, MA, USA, 1986. Google Scholar
Digital Library
- Atmel. Avr 8-bit and 32-bit microcontroller, 2013. URL www.atmel.com/products/microcontrollers/avr/.Google Scholar
- T. Austin, E. Larson, and D. Ernst. Simplescalar: An infrastructure for computer system modeling. Computer, pages 59--67, 2002. Google Scholar
Digital Library
- M. Awasthi, M. Shevgoor, K. Sudan, B. Rajendran, R. Balasubramonian, and V. Srinivasan. Efficient scrub mechanisms for error-prone emerging memories. In phHPCA, 2012. Google Scholar
Digital Library
- G. Balakrishnan and T. Reps. Analyzing memory accesses in x86 executables. In CC, 2004.Google Scholar
- Y. Choi, I. Song, and M.-H. Park. A 20nm 1.8v 8gb pram with 40mb/s program bandwidth. In ISSCC, 2012.Google Scholar
- H. Falk and J. Kleinsorge. Optimal static wcet-aware scratchpad allocation of program code. In phDAC, 2009. Google Scholar
Digital Library
- Freescale. MC13224V Technical Data, 2012.Google Scholar
- L. M. Grupp, J. D. Davis, and S. Swanson. The bleak future of nand flash memory. In FAST, 2012. Google Scholar
Digital Library
- A. Hay, K. Strauss, T. Sherwood, G. Loh, and D. Burger. Preventing pcm banks from seizing too much power. In MICRO, 2011. Google Scholar
Digital Library
- J. Hu, C. Xue, W.-C. Tseng, Q. Zhuge, and E.-M. Sha. Minimizing write activities to non-volatile memory via scheduling and recomputation. In SASP, pages 101--106, 2010. Google Scholar
Digital Library
- J. Hu, W.-C. Tseng, C. Xue, Q. Zhuge, Y. Zhao, and E.-M. Sha. Write activity minimization for nonvolatile main memory via scheduling and recomputation. phComputer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 30 (4): 584--592, 2011. ISSN 0278-0070. Google Scholar
Digital Library
- L. Jiang, Y. Zhang, and J. Yang. Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling. In ISLPED, 2011. Google Scholar
Digital Library
- L. Jiang, Y. Zhang, B. R. Childers, and J. Yang. Fpb: Fine-grained power budgeting to improve write throughput of multi-level cell phase change memory. In MICRO, 2012. Google Scholar
Digital Library
- L. Jiang, Y. Zhang, and J. Yang. Er: elastic reset for low power and long endurance mlc based phase change memory. In ISLPED, 2012. Google Scholar
Digital Library
- L. Jiang, B. Zhao, Y. Zhang, J. Yang, and B. R. Childers. Improving write operations in mlc phase change memory. In HPCA, 2012. Google Scholar
Digital Library
- M. Joshi, W. Zhang, and T. Li. Mercury: A fast and energy-efficient multi-level cell based phase change memory system. In HPCA, 2011. Google Scholar
Digital Library
- C.-M. Jung, E.-S. Lee, K.-S. Min, and S.-M. S. Kang. Compact verilog-a model of phase-change ram transient behaviors for multi-level applications. In Semiconductor Science and Technology, volume 25, 2011.Google Scholar
Cross Ref
- C. e. Lattner. The llvm compiler infrastructure, 2012. URL http://llvm.org/.Google Scholar
- B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting phase change memory as a scalable dram alternative. In ISCA, 2009. Google Scholar
Digital Library
- J. Li, L. Shi, C. Xue, C. Yang, and Y. Xu. Exploiting set-level write non-uniformity for energy-efficient nvm-based hybrid cache. In phEmbedded Systems for Real-Time Multimedia (ESTIMedia), 2011 9th IEEE Symposium on, pages 19--28, 2011.Google Scholar
- J. Li, C. Xue, and Y. Xu. Stt-ram based energy-efficiency hybrid cache for cmps. In VLSI-SoC, pages 31--36, 2011.Google Scholar
Cross Ref
- X. Li, Y. Liang, T. Mitra, and A. Roychoudury. Chronos: A timing analyzer for embedded software. phScience of Computer Programming, 69 (1--3): 56--67. Google Scholar
Digital Library
- J.-T. Lin, Y.-B. Liao, M.-H. Chiang, I.-H. Chiu, C.-L. Lin, W.-C. Hsu, P.-C. Chiang, S.-S. Sheu, Y.-Y. Hsu, W.-H. Liu, K.-L. Su, M.-J. Kao, and M.-J. Tsai. Design optimization in write speed of multi-level cell application for phase change memory. In EDSSC, 2009.Google Scholar
- T. Liu, M. Li, and C. Xue. Minimizing wcet for real-time embedded systems via static instruction cache locking. In RTAS, 2009. Google Scholar
Digital Library
- T. Liu, Y. Zhao, C. Xue, and M. Li. Power-aware variable partitioning for dsps with hybrid pram and dram main memory. In DAC, pages 405--410, 2011. Google Scholar
Digital Library
- D. Mantegazza, D. Ielmini, E. Varesi, A. Pirovano, and A. Lacaita. Statistical analysis and modeling of programming and retention in pcm arrays. In IEDM, 2007.Google Scholar
Cross Ref
- Micro. PCM chip, 2012. URL http://www.micron.com/products/multichip-packages/pcm-based-mcp.Google Scholar
- Microchip. Pic microcontrollers, 2013. URL www.microchip.com/pagehandler/en-us/products/picmicrocontrollers.Google Scholar
- OracleLabs. SunSPOT, 2012. URL www.sunspotworld.com/.Google Scholar
- Z. Qin, Y. Wang, D. Liu, and Z. Shao. Demand-based block-level address mapping in large-scale nand flash storage systems. In phCODES/ISSS, CODES/ISSS '10, pages 173--182, New York, NY, USA, 2010. ACM. ISBN 978--1--60558--905--3. Google Scholar
Digital Library
- Z. Qin, Y. Wang, D. Liu, Z. Shao, and Y. Guan. Mnftl: an efficient flash translation layer for mlc nand flash memory storage systems. In DAC, DAC '11, pages 17--22, New York, NY, USA, 2011. ACM. ISBN 978--1--4503-0636--2. Google Scholar
Digital Library
- M. K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali. Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling. In MICRO, 2009. Google Scholar
Digital Library
- M. K. Qureshi, V. Srinivasan, and J. A. Rivers. Scalable high performance main memory system using phase-change memory technology. In ISCA, 2009. Google Scholar
Digital Library
- M. K. Qureshi, M. M. Franceschini, and L. A. Lastras-Montano. Improving read performance of phase change memories via write cancellation and write pausing. In HPCA, 2010.Google Scholar
Cross Ref
- M. K. Qureshi, M. M. Franceschini, L. A. Lastras-Montano, and J. P. Karidis. Morphable memory system: A robust architecture for exploiting multi-level phase change memories. In phISCA, 2010. Google Scholar
Digital Library
- M. K. Qureshi, M. Franceschini, L. Lastras, and A. Jagmohan. Preset: Improving read write performance of phase change memories by exploiting asymmetry in write times. In ISCA, 2012. Google Scholar
Digital Library
- S. Raoux, G. W. Burr, M. J. Breitwisch, C. T. Rettner, Y.-C. Chen, R. M. Shelby, M. Salinga, D. Krebs, S.-H. Chen, H.-L. Lung, and C. H. Lam. Phase-change random access memory: A scalable technology. IBM J. RES. & DEV., 2008. Google Scholar
Digital Library
- T. Reps and G. Balakrishnan. Improved memory-access analysis for x86 executables. In CC, 2008. Google Scholar
Digital Library
- L. Shi, C. J. Xue, J. Hu, W.-C. Tseng, X. Zhou, and E. H.-M. Sha. Write activity reduction on flash main memory via smart victim cache. In phGLSVLSI, GLSVLSI'0, pages 91--94, New York, NY, USA, 2010. ACM. ISBN 978--1--4503-0012--4. Google Scholar
Digital Library
- V. Suhendra, T. Mitra, A. Roychoudhury, and T. Chen. Wcet centric data allocation to scratchpad memory. In RTSS, 2005. Google Scholar
Digital Library
- X. Vera, B. Lisper, and J. Xue. Data cache locking for tight timing calculations. ACM Trans. Embed. Comput. Syst., 2007. Google Scholar
Digital Library
- R. e. Wilhelm. The worst-case execution-time problemoverview of methods and survey of tools. ACM Trans. Embed. Comput. Syst., 2008. Google Scholar
Digital Library
- W. Zhang and T. Li. Characterizing and mitigating the impact of process variations on phase change based memory systems. In MICRO, 2009. Google Scholar
Digital Library
- W. Zhang and T. Li. Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system. In DSN, 2011. Google Scholar
Digital Library
- P. Zhou, B. Zhao, J. Yang, and Y. Zhang. A durable and energy efficient main memory using phase change memory technology. In ISCA, 2009. Google Scholar
Digital Library
- P. Zhou, Y. Zhang, and J. Yang. The design of sustainable wireless sensor network node using solar energy and phase change memory. In DATE, 2013. Google Scholar
Digital Library
Index Terms
Compiler directed write-mode selection for high performance low power volatile PCM
Recommendations
Compiler directed write-mode selection for high performance low power volatile PCM
LCTES '13: Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systemsMicro-Controller Units (MCUs) are widely adopted ubiquitous computing devices. Due to tight cost and energy constraints, MCUs often integrate very limited internal RAM memory on top of Flash storage, which exposes Flash to heavy write traffic and ...
Compiler directed write-mode selection for high performance low power volatile PCM
LCTES '13: Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systemsMicro-Controller Units (MCUs) are widely adopted ubiquitous computing devices. Due to tight cost and energy constraints, MCUs often integrate very limited internal RAM memory on top of Flash storage, which exposes Flash to heavy write traffic and ...
Power-Utility-Driven Write Management for MLC PCM
Special Issue on Hardware and Algorithms for Learning On-a-chip and Special Issue on Alternative Computing SystemsPhase change memory (PCM) is a promising alternative to Dynamic Random Access Memory (DRAM) as main memory due to its merits of high density and low leakage power. Multi-level Cell (MLC) PCM is more attractive than Single-level Cell (SLC) PCM, because ...







Comments