skip to main content
research-article

Compiler directed write-mode selection for high performance low power volatile PCM

Authors Info & Claims
Published:20 June 2013Publication History
Skip Abstract Section

Abstract

Micro-Controller Units (MCUs) are widely adopted ubiquitous computing devices. Due to tight cost and energy constraints, MCUs often integrate very limited internal RAM memory on top of Flash storage, which exposes Flash to heavy write traffic and results in short system lifetime. Architecting emerging Phase Change Memory (PCM) is a promising approach for MCUs due to its fast read speed and long write endurance.

However, PCM, especially multi-level cell (MLC) PCM, has long write latency and requires large write energy, which diminishes the benefits of its replacement of traditional Flash. By studying MLC PCM write operations, we observe that writing MLC PCM can take advantages of two write modes --- fast write leaves cells in volatile state, and slow write leaves cells in non-volatile state. In this paper, we propose a compiler directed dual-write (CDDW) scheme that selects the best write mode for each write operation to maximize the overall performance and energy efficiency. Our experimental results show that CDDW reduces dynamic energy by 32.4%(33.8%) and improves performance by 6.3%(35.9%) compared with an all fast(slow) write approach.

References

  1. AbsInt. ait worst-case execution time analyzers, 2013. URL http://www.absint.com/ait/index.htm.Google ScholarGoogle Scholar
  2. A. V. Aho, R. Sethi, and J. D. Ullman. phCompilers: principles, techniques, and tools. Addison-Wesley Longman Publishing Co., Inc., Boston, MA, USA, 1986. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Atmel. Avr 8-bit and 32-bit microcontroller, 2013. URL www.atmel.com/products/microcontrollers/avr/.Google ScholarGoogle Scholar
  4. T. Austin, E. Larson, and D. Ernst. Simplescalar: An infrastructure for computer system modeling. Computer, pages 59--67, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. M. Awasthi, M. Shevgoor, K. Sudan, B. Rajendran, R. Balasubramonian, and V. Srinivasan. Efficient scrub mechanisms for error-prone emerging memories. In phHPCA, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. G. Balakrishnan and T. Reps. Analyzing memory accesses in x86 executables. In CC, 2004.Google ScholarGoogle Scholar
  7. Y. Choi, I. Song, and M.-H. Park. A 20nm 1.8v 8gb pram with 40mb/s program bandwidth. In ISSCC, 2012.Google ScholarGoogle Scholar
  8. H. Falk and J. Kleinsorge. Optimal static wcet-aware scratchpad allocation of program code. In phDAC, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Freescale. MC13224V Technical Data, 2012.Google ScholarGoogle Scholar
  10. L. M. Grupp, J. D. Davis, and S. Swanson. The bleak future of nand flash memory. In FAST, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. A. Hay, K. Strauss, T. Sherwood, G. Loh, and D. Burger. Preventing pcm banks from seizing too much power. In MICRO, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. J. Hu, C. Xue, W.-C. Tseng, Q. Zhuge, and E.-M. Sha. Minimizing write activities to non-volatile memory via scheduling and recomputation. In SASP, pages 101--106, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. J. Hu, W.-C. Tseng, C. Xue, Q. Zhuge, Y. Zhao, and E.-M. Sha. Write activity minimization for nonvolatile main memory via scheduling and recomputation. phComputer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 30 (4): 584--592, 2011. ISSN 0278-0070. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. L. Jiang, Y. Zhang, and J. Yang. Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling. In ISLPED, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. L. Jiang, Y. Zhang, B. R. Childers, and J. Yang. Fpb: Fine-grained power budgeting to improve write throughput of multi-level cell phase change memory. In MICRO, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. L. Jiang, Y. Zhang, and J. Yang. Er: elastic reset for low power and long endurance mlc based phase change memory. In ISLPED, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. L. Jiang, B. Zhao, Y. Zhang, J. Yang, and B. R. Childers. Improving write operations in mlc phase change memory. In HPCA, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. M. Joshi, W. Zhang, and T. Li. Mercury: A fast and energy-efficient multi-level cell based phase change memory system. In HPCA, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. C.-M. Jung, E.-S. Lee, K.-S. Min, and S.-M. S. Kang. Compact verilog-a model of phase-change ram transient behaviors for multi-level applications. In Semiconductor Science and Technology, volume 25, 2011.Google ScholarGoogle ScholarCross RefCross Ref
  20. C. e. Lattner. The llvm compiler infrastructure, 2012. URL http://llvm.org/.Google ScholarGoogle Scholar
  21. B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting phase change memory as a scalable dram alternative. In ISCA, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. J. Li, L. Shi, C. Xue, C. Yang, and Y. Xu. Exploiting set-level write non-uniformity for energy-efficient nvm-based hybrid cache. In phEmbedded Systems for Real-Time Multimedia (ESTIMedia), 2011 9th IEEE Symposium on, pages 19--28, 2011.Google ScholarGoogle Scholar
  23. J. Li, C. Xue, and Y. Xu. Stt-ram based energy-efficiency hybrid cache for cmps. In VLSI-SoC, pages 31--36, 2011.Google ScholarGoogle ScholarCross RefCross Ref
  24. X. Li, Y. Liang, T. Mitra, and A. Roychoudury. Chronos: A timing analyzer for embedded software. phScience of Computer Programming, 69 (1--3): 56--67. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. J.-T. Lin, Y.-B. Liao, M.-H. Chiang, I.-H. Chiu, C.-L. Lin, W.-C. Hsu, P.-C. Chiang, S.-S. Sheu, Y.-Y. Hsu, W.-H. Liu, K.-L. Su, M.-J. Kao, and M.-J. Tsai. Design optimization in write speed of multi-level cell application for phase change memory. In EDSSC, 2009.Google ScholarGoogle Scholar
  26. T. Liu, M. Li, and C. Xue. Minimizing wcet for real-time embedded systems via static instruction cache locking. In RTAS, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. T. Liu, Y. Zhao, C. Xue, and M. Li. Power-aware variable partitioning for dsps with hybrid pram and dram main memory. In DAC, pages 405--410, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. D. Mantegazza, D. Ielmini, E. Varesi, A. Pirovano, and A. Lacaita. Statistical analysis and modeling of programming and retention in pcm arrays. In IEDM, 2007.Google ScholarGoogle ScholarCross RefCross Ref
  29. Micro. PCM chip, 2012. URL http://www.micron.com/products/multichip-packages/pcm-based-mcp.Google ScholarGoogle Scholar
  30. Microchip. Pic microcontrollers, 2013. URL www.microchip.com/pagehandler/en-us/products/picmicrocontrollers.Google ScholarGoogle Scholar
  31. OracleLabs. SunSPOT, 2012. URL www.sunspotworld.com/.Google ScholarGoogle Scholar
  32. Z. Qin, Y. Wang, D. Liu, and Z. Shao. Demand-based block-level address mapping in large-scale nand flash storage systems. In phCODES/ISSS, CODES/ISSS '10, pages 173--182, New York, NY, USA, 2010. ACM. ISBN 978--1--60558--905--3. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. Z. Qin, Y. Wang, D. Liu, Z. Shao, and Y. Guan. Mnftl: an efficient flash translation layer for mlc nand flash memory storage systems. In DAC, DAC '11, pages 17--22, New York, NY, USA, 2011. ACM. ISBN 978--1--4503-0636--2. Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. M. K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali. Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling. In MICRO, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. M. K. Qureshi, V. Srinivasan, and J. A. Rivers. Scalable high performance main memory system using phase-change memory technology. In ISCA, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. M. K. Qureshi, M. M. Franceschini, and L. A. Lastras-Montano. Improving read performance of phase change memories via write cancellation and write pausing. In HPCA, 2010.Google ScholarGoogle ScholarCross RefCross Ref
  37. M. K. Qureshi, M. M. Franceschini, L. A. Lastras-Montano, and J. P. Karidis. Morphable memory system: A robust architecture for exploiting multi-level phase change memories. In phISCA, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  38. M. K. Qureshi, M. Franceschini, L. Lastras, and A. Jagmohan. Preset: Improving read write performance of phase change memories by exploiting asymmetry in write times. In ISCA, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  39. S. Raoux, G. W. Burr, M. J. Breitwisch, C. T. Rettner, Y.-C. Chen, R. M. Shelby, M. Salinga, D. Krebs, S.-H. Chen, H.-L. Lung, and C. H. Lam. Phase-change random access memory: A scalable technology. IBM J. RES. & DEV., 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  40. T. Reps and G. Balakrishnan. Improved memory-access analysis for x86 executables. In CC, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  41. L. Shi, C. J. Xue, J. Hu, W.-C. Tseng, X. Zhou, and E. H.-M. Sha. Write activity reduction on flash main memory via smart victim cache. In phGLSVLSI, GLSVLSI'0, pages 91--94, New York, NY, USA, 2010. ACM. ISBN 978--1--4503-0012--4. Google ScholarGoogle ScholarDigital LibraryDigital Library
  42. V. Suhendra, T. Mitra, A. Roychoudhury, and T. Chen. Wcet centric data allocation to scratchpad memory. In RTSS, 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  43. X. Vera, B. Lisper, and J. Xue. Data cache locking for tight timing calculations. ACM Trans. Embed. Comput. Syst., 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  44. R. e. Wilhelm. The worst-case execution-time problemoverview of methods and survey of tools. ACM Trans. Embed. Comput. Syst., 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  45. W. Zhang and T. Li. Characterizing and mitigating the impact of process variations on phase change based memory systems. In MICRO, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  46. W. Zhang and T. Li. Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system. In DSN, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  47. P. Zhou, B. Zhao, J. Yang, and Y. Zhang. A durable and energy efficient main memory using phase change memory technology. In ISCA, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  48. P. Zhou, Y. Zhang, and J. Yang. The design of sustainable wireless sensor network node using solar energy and phase change memory. In DATE, 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Compiler directed write-mode selection for high performance low power volatile PCM

        Recommendations

        Comments

        Login options

        Check if you have access through your login credentials or your institution to get full access on this article.

        Sign in

        Full Access

        • Published in

          cover image ACM SIGPLAN Notices
          ACM SIGPLAN Notices  Volume 48, Issue 5
          LCTES '13
          May 2013
          165 pages
          ISSN:0362-1340
          EISSN:1558-1160
          DOI:10.1145/2499369
          Issue’s Table of Contents
          • cover image ACM Conferences
            LCTES '13: Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
            June 2013
            184 pages
            ISBN:9781450320856
            DOI:10.1145/2491899

          Copyright © 2013 ACM

          Publisher

          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 20 June 2013

          Check for updates

          Qualifiers

          • research-article

        PDF Format

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader
        About Cookies On This Site

        We use cookies to ensure that we give you the best experience on our website.

        Learn more

        Got it!