Abstract
The continual trend of shrinking feature sizes and reducing voltage levels makes transistors faster and more efficient. However, it also makes them more susceptible to transient hardware faults. Transient faults due to high energy particle strikes or circuit crosstalk can corrupt the output of a program or cause it to crash. Previous studies have reported that as much as 70% of the transient faults disturb program control flow, making it critical to protect control flow. Traditional approaches employ signatures to check that every control flow transfer in a program is valid. While having high fault coverage, large performance overheads are introduced by such detailed checking. We propose a coarse-grain control flow checking method to detect transient faults in a cost effective way. Our software-only approach is centered on the principle of abstraction: control flow that exhibits simple run-time properties (e.g., proper path length) is almost always completely correct. Our solution targets off-the-shelf commodity embedded systems to provide a low cost protection against transient faults. The proposed technique achieves its efficiency by simplifying signature calculations in each basic block and by performing checking at a coarse-grain level. The coarse-grain signature comparison points are obtained by the use of a region based analysis. In addition, we propose a technique to protect control flow transfers via call and return instructions to ensure all control flow is covered by our technique. Overall, our proposed technique has an average of 11% performance overhead in comparison to 75% performance overhead of previously proposed signature based techniques while maintaining approximately the same degree of fault coverage.
- M. Abadi, M. Budiu, U. Erlingsson, and J. Ligatti. Control-flow integrity principles, implementations, and applications. ACM Trans. Inf. Syst. Secur., 13 (1): 4:1--4:40, Nov. 2009. ISSN 1094--9224. Google Scholar
Digital Library
- A. Aho, M. Lam, R. Sethi, and J. Ullman. Compilers: principles, techniques, and tools, volume 1009. Pearson/Addison Wesley, 2007. Google Scholar
Digital Library
- Z. Alkhalifa, V. Nair, N. Krishnamurthy, and J. Abraham. Design and evaluation of system-level checks for on-line control flow error detection. TDPS, jun 1999. Google Scholar
Digital Library
- T. Ball and J. R. Larus. Efficient path profiling. In ACM/IEEE Micro, 1996. Google Scholar
Digital Library
- W. Bartlett and L. Spainhower. Commercial fault tolerance: A tale of two systems. In TDSC, pages 87--96, 2004. Google Scholar
Digital Library
- D. Bernick, B. Bruckert, P. D. Vigna, D. Garcia, R. Jardine, J. Klecka, and J. Smullen. Nonstop advanced architecture. In DSN, pages 12--21, June 2005. Google Scholar
Digital Library
- N. Binkert et al. The gem5 simulator. SIGARCH Comput. Archit. News, 39 (2), Aug. 2011. Google Scholar
Digital Library
- E. Borin, C. Wang, Y. Wu, and G. Araujo. Software-based transparent and comprehensive control-flow error detection. In CGO, 2006. Google Scholar
Digital Library
- M. Chu, K. Fan, and S. Mahlke. Region-based hierarchical operation partitioning for multicluster processors. In PLDI, pages 300--311, June 2003. Google Scholar
Digital Library
- S. Feng, S. Gupta, A. Ansari, and S. Mahlke. Shoestring: Probabilistic soft-error reliability on the cheap. In ASPLOS, Mar. 2010. Google Scholar
Digital Library
- S. Feng, S. Gupta, A. Ansari, S. A. Mahlke, and D. I. August. Encore: low-cost, fine-grained transient fault recovery. In MICRO, pages 398--409, 2011. Google Scholar
Digital Library
- B. T. Gold, J. C. Smolens, B. Falsafi, and J. C. Hoe. The granularity of soft-error containment in shared memory multiprocessors. IEEE Workshop on SELSE, 2006.Google Scholar
- O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, and M. Violante. Soft-error detection using control flow assertions. In DFT, pages 581 -- 588, nov. 2003. Google Scholar
Digital Library
- M. Gomaa and T. Vijaykumar. Opportunistic transient-fault detection. In ISCA, pages 172--183, June 2005. Google Scholar
Digital Library
- D. S. Khudia, G. Wright, and S. Mahlke. Efficient soft error protection for commodity embedded microprocessors using profile information. In LCTES, pages 99--108, New York, NY, USA, 2012. ACM. Google Scholar
Digital Library
- C. Lattner and V. Adve. LLVM: A compilation framework for lifelong program analysis & transformation. In CGO, pages 75--86, 2004. Google Scholar
Digital Library
- R. Leveugle, A. Calvez, P. Maistri, and P. Vanhauwaert. Statistical fault injection: quantified error and confidence. In DATE, pages 502--506, 2009. Google Scholar
Digital Library
- M. Li, M. Pradeep, R. S. Sahoo, S. Adve, V. Adve, and Y. Y. Zhou. Swat: An error resilient system. In IEEE Workshop on SELSE, pages 8--13, 2008.Google Scholar
- X. Li and J.-L. Gaudiot. A compiler-assisted on-chip assigned-signature control flow checking. In Advances in Computer Systems Architecture, volume 3189 of LNCS, pages 554--567. Springer Berlin, 2004.Google Scholar
Cross Ref
- X. Li and D. Yeung. Application-level correctness and its impact on fault tolerance. In HPCA, pages 181--192, Feb. 2007. Google Scholar
Digital Library
- D. Lu. Watchdog processors and structural integrity checking. IEEE Transactions on Computers, C-31 (7): 681--685, july 1982. Google Scholar
Digital Library
- A. Mahmood and E. J. McCluskey. Concurrent error detection using watchdog processors-a survey. IEEE Trans. Comput., 37 (2): 160--174, Feb. 1988. Google Scholar
Digital Library
- T. May and M. Woods. Alpha-particle-induced soft errors in dynamic memories. IEEE Transactions on Electron Devices, 26 (1): 2--9, Jan. 1979.Google Scholar
- A. Meixner, M. Bauer, and D. Sorin. Argus: Low-cost, comprehensive error detection in simple cores. IEEE Micro, 28 (1): 52--59, 2008. Google Scholar
Digital Library
- T. Michel, R. Leveugle, and G. Saucier. A new approach to control flow checking without program modification. In FTC, pages 334 --341, jun 1991.Google Scholar
Cross Ref
- S. Muchnick. Advanced Compiler Design Implementation. Morgan Kaufmann Publishers, 1997. Google Scholar
Digital Library
- S. Mukherjee. Architecture Design for Soft Errors. Morgan Kaufmann, 2008. Google Scholar
Digital Library
- S. S. Mukherjee, C. Weaver, J. Emer, S. Reinhardt, and T. Austin. A systematic methodology to compute the architectural vulnerability factors for a high performance microprocessor. In MICRO, pages 29--42, Dec. 2003. Google Scholar
Digital Library
- N. Oh, P. Shirvani, and E. McCluskey. Control-flow checking by software signatures. IEEE Transactions on Reliability, 51 (1): 111 --122, mar 2002.Google Scholar
Cross Ref
- N. Oh, P. Shirvani, and E. McCluskey. Error detection by duplicated instructions in super-scalar processors. Reliability, IEEE Transactions on, 51 (1): 63--75, 2002. Google Scholar
Digital Library
- S. K. Reinhardt and S. S. Mukherjee. Transient fault detection via simulataneous multithreading. In Proc. of the 27th ISCA, pages 25--36, June 2000. Google Scholar
Digital Library
- G. Reis, J. Chang, N. Vachharajani, R. Rangan, and D. I. August. SWIFT: Software implemented fault tolerance. In CGO, pages 243--254, 2005. Google Scholar
Digital Library
- G. A. Reis, J. Chang, N. Vachharajani, R. Rangan, D. I. August, and S. S. Mukherjee. Software-controlled fault tolerance. ACM TACO, 2 (4): 366--396, 2005. Google Scholar
Digital Library
- E. Rotenberg. AR-SMT: A microarchitectural approach to fault tolerance in microprocessors. In International Symposium on Fault Tolerant Computing, 1999. Google Scholar
Digital Library
- P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi. Modeling the effect of technology trends on the soft error rate of combinational logic. In DSN, pages 389--398, June 2002. Google Scholar
Digital Library
- R. Vemu and J. Abraham. Ceda: Control-flow error detection using assertions. IEEE Transactions on Computers, 60 (9): 1233--1245, sept. 2011. Google Scholar
Digital Library
- R. Venkatasubramanian, J. Hayes, and B. Murray. Low-cost on-line fault detection using control flow assertions. In IOLTS 2003., july 2003.Google Scholar
Cross Ref
- N. J. Wang and S. J. Patel. ReStore: Symptom-based soft error detection in microprocessors. In TDSC, 3 (3): 188--201, June 2006. Google Scholar
Digital Library
- N. J. Wang, J. Quek, T. M. Rafacz, and S. J. Patel. Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline. In DSN, June 2004. Google Scholar
Digital Library
- J. F. Ziegler and H. Puchner. SER-History, Trends, and Challenges: A Guide for Designing with Memory ICs. Cypress Semiconductor Corp., 2004.Google Scholar
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Low cost control flow protection using abstract control signatures
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