Abstract
We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and the connection and the switch block flexibilities. The output is an estimate of the proportion of nets in a large circuit that can be expected to be successfully routed on the FPGA. We assume that the circuit is routed to the FPGA using a single-step combined global/detailed router. We show that the model correctly predicts routability trends. We also present an example application to demonstrate that this model may be a valuable tool for FPGA architects. When combined with the earlier works on analytical modeling, our model can be used to quickly predict the routability without going through any stage of an expensive CAD flow. We envisage that this model will benefit FPGA architecture designers and vendors to quickly evaluate FPGA routing fabrics.
- Ahmed, E. and Rose, J. 2004. The effect of lut and cluster size on deep-submicron fpga performance and density. IEEE Trans. VLSI 12, 3, 288--298. Google Scholar
Digital Library
- Altera Corp. 2010. Press release: Altera unveils 28-nm stratix v fpga family. (4/19/10).Google Scholar
- Ball, M. O. 1986. Computational complexity of network reliability analysis: An overview. IEEE Trans. Reliabil. 35, 3, 230--239.Google Scholar
Cross Ref
- Betz, V., Rose, J., and Marquardt, A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers. Google Scholar
Digital Library
- Brown, S. D., Rose, J., and Vranesic, Z. Dec. 1993. A stochastic model to predict the routability of field-programmable gate arrays. IEEE Trans. Comput. Aid. Des. Circ. Syst. 12, 12, 1827--1838. Google Scholar
Digital Library
- Cheng, C. E. 1994. Risa: Accurate and efficient placement routability modeling. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'94). 690--695. Google Scholar
Digital Library
- Christie, P. and Stroobandt, D. 2000. The interpretation and application of rent's rule. IEEE Trans. VLSI 8, 6, 639--648. Google Scholar
Digital Library
- Colbourn, C. J. 1987. The Combinatorics of Network Reliability. Oxford University Press, New York. Google Scholar
Digital Library
- Colbourn, C. J. 1991. Combinatorial aspects of network reliability. Ann. Oper. Res. 33, 1, 1--15.Google Scholar
Cross Ref
- Das, J., Lam, A., Wilton, S., Leong, P., and Luk, W. 2011. An analytical model relating fpga architecture to logic density and depth. IEEE Trans. VLSI 19, 12, 2229--2242. Google Scholar
Digital Library
- Das, J., Wilton, S., Leong, P., and Luk, W. 2009. Modeling post-techmapping and post-clustering fpga circuit depth. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'09). 205--211.Google Scholar
- Das, J. and Wilton, S. J. 2011a. Accelerated fpga architecture design: Capabilities and limitations of analytical model. In Proceedings of the International Conference on Field Programmable Technology (FPT'11).Google Scholar
- Das, J. and Wilton, S. J. 2011b. An analytical model relating fpga architecture parameters to routability. In Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'11). ACM Press, New York, 181--184. Google Scholar
Digital Library
- Davis, J., De, V., and Meindl, J. M. 1998. A stochastic wire-length distribution for gigascale integration (gsi). Part I. Derivation and validation. IEEE Trans. Elec. Devices 45, 3, 580--589.Google Scholar
Cross Ref
- El Gamal, A. A. Feb. 1981. Two-dimensional stochastic models for interconnections in master-slice integrated circuits. IEEE Trans. Circ. Syst. 26, 4, 127--138.Google Scholar
Cross Ref
- Elmallah, E. and Aboelfotoh, H. 2006. Circular layout cutsets: An approach for improving consecutive cutset bounds for network reliability. IEEE Trans. Reliabil. 55, 4, 602--612.Google Scholar
Cross Ref
- Fang, W. M. and Rose, J. 2008. Modeling routing demand for early-stage fpga architecture development. In Proceedings of the 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'08). ACM Press, New York, 139--148. Google Scholar
Digital Library
- Hung, E., Wilton, S. J. E., Yu, H., Chau, T. C. P., and Leong, P. H. W. 2009. An analytical fpga delay path model. In Proceedings of the International Conference on Field Programmable Technology (FPT'09).Google Scholar
- Kannan, P., Balachandran, S., and Bhatia, D. 2001. fGREP - Fast generic routing demand estimation for placed fpga circuits. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'01). 37--47. Google Scholar
Digital Library
- Lam, A., Wilton, S. J. E., Leong, P., and Luk, W. 2008. An analytical model describing the relationships between logic architecture and fpga density. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'08). 221--226.Google Scholar
- Lemieux, G. G. F., Brown, S. D., and Vranesic, D. 1997. On two-step routing for fpgas. In Proceedings of the International Symposium on Physical Design (ISPD'97). ACM Press, New York, 60--66. Google Scholar
Digital Library
- Lou, J., Krishnamoorthy, S., and Sheng, H. S. 2001. Estimating routing congestion using probabilistic analysis. In Proceedings of the International Symposium on Physical Design (ISPD'01). ACM Press, New York, 112--117. Google Scholar
Digital Library
- Luu, J., Kuon, I., Jamieson, P., Campbell, T., Ye, A., Fang, W. M., and Rose, J. 2009. VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. In Proceedings of the 17th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'09). 133--142. Google Scholar
Digital Library
- Mcmurchie, L. and Ebeling, C. 1995. Pathfinder: A negotiation-based performance-driven router for fpgas. In Proceedings of the 3rd ACM International Symposium on Field-Programmable Gate Arrays (FPGA'95). ACM Press, New York, 111--117. Google Scholar
Digital Library
- Provan, J. S. and Ball, M. O. 1984. Computing network reliability in time polynomial in the number of cuts. Oper. Res. 32, 3, 516--526.Google Scholar
Digital Library
- Quip. 2013. Altera corp.: Quartus II university interface program (quip) toolkit. http://www.altera.com/education/univ/research/quip/unv-quip.html.Google Scholar
- Rahman, A., Fan, A., and Reif, R. 1999. Wire-length distribution of three-dimensional integrated circuit. In Proceedings of the International Workshop on System Level Interconnect Prediction (SLIP'99).Google Scholar
- Shanthikumar, J. 1988. Bounding network-reliability using consecutive minimal cutsets. IEEE Trans. Reliab. 37, 1, 45--49.Google Scholar
Cross Ref
- Shanthikumar, J. G. 1987. Reliability of systems with consecutive minimal cutsets. IEEE Trans. Reliab. R-36, 5, 546--550.Google Scholar
Cross Ref
- Shyu, M.,Wu, G.-M., Chang, Y.-D., and Chang, Y.-W. 2000. Generic universal switch blocks. IEEE Trans. Comput. 49, 4, 348--359. Google Scholar
Digital Library
- Singh, A., Parthasarathy, G., and Marek-Sadowska, M. 2001. Interconnect resource-aware placement for hierarchical fpgas. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'01). 132--136. Google Scholar
Digital Library
- Smith, A. M., Constantinides, G. A., Wilton, S. J. E., and Cheung, P. Y. K. 2009a. Concurrently optimizing fpgs architecture parameters and transistor sizing: Implications for fpga design. In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT'09).Google Scholar
- Smith, A. M., Wilton, S. J., and Das, J. 2009b. Wirelength modeling for homogeneous and heterogeneous fpga architectural development. In Proceedings of the 17th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'09). ACM Press, New York, 181--190. Google Scholar
Digital Library
- U Of Toronto. 2009. VPR and t-vpack user's manual. http://www.eecg.utoronto.ca/vpr/VPR_5.pdf.Google Scholar
- Wilton, S. J. E. 1997. Architectures and algorithms for field-programmable gate arrays with embedded memory. Ph.D. thesis, University of Toronto, Ontario, Canada. Google Scholar
Digital Library
- Wood, R. G. and Rutenbar, R. A. 1997. FPGA routing and routability estimation via boolean satisfiability. In Proceedings of the 5th ACM International Symposium on Field-Programmable Gate Arrays (FPGA'97). Google Scholar
Digital Library
- Wu, Y.-L. and Marek-Sadowska, M. 1994. An efficient router for 2-d field programmable gate array. In Proceedings of the European Design and Test Conference. 412--416.Google Scholar
- Xilinx Inc. 2010. Press Release: Xilinx 7 series fpgss slash power consumption by 50% and reach 2 million logic cells on industrys first scalable architecture (6/21/10).Google Scholar
- Yang, S. 1991. Logic synthesis and optimization benchmarks user guide version 3.0. Tech. rep., Microcenter of North Carolina. http://www.researchgate.net/publication/2404650_Logic_Synthesis_and_Optimization_Benchmarks_User_Guide_Version_3.0.Google Scholar
- Zhu, Y., Hu, Y., Taylor, M. B., and Cheng, C.-K. 2009. Energy and switch area optimizations for FPGA global routing architectures. ACM Trans. Des. Autom. Electron. Syst. 14, 13:1--13:25. Google Scholar
Digital Library
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Towards development of an analytical model relating FPGA architecture parameters to routability
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