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Towards development of an analytical model relating FPGA architecture parameters to routability

Published:02 August 2013Publication History
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Abstract

We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and the connection and the switch block flexibilities. The output is an estimate of the proportion of nets in a large circuit that can be expected to be successfully routed on the FPGA. We assume that the circuit is routed to the FPGA using a single-step combined global/detailed router. We show that the model correctly predicts routability trends. We also present an example application to demonstrate that this model may be a valuable tool for FPGA architects. When combined with the earlier works on analytical modeling, our model can be used to quickly predict the routability without going through any stage of an expensive CAD flow. We envisage that this model will benefit FPGA architecture designers and vendors to quickly evaluate FPGA routing fabrics.

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      • Published in

        cover image ACM Transactions on Reconfigurable Technology and Systems
        ACM Transactions on Reconfigurable Technology and Systems  Volume 6, Issue 2
        Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
        July 2013
        90 pages
        ISSN:1936-7406
        EISSN:1936-7414
        DOI:10.1145/2499625
        Issue’s Table of Contents

        Copyright © 2013 ACM

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 2 August 2013
        • Accepted: 1 January 2013
        • Revised: 1 November 2012
        • Received: 1 March 2012
        Published in trets Volume 6, Issue 2

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