skip to main content
research-article

Parallel architectures for the kNN classifier -- design of soft IP cores and FPGA implementations

Published:30 September 2013Publication History
Skip Abstract Section

Abstract

We designed a variety of k-nearest-neighbor parallel architectures for FPGAs in the form of parameterizable soft IP cores. We show that they can be used to solve large classification problems with thousands of training vectors, or thousands of vector dimensions using a single FPGA, and achieve very high throughput. They can be used to flexibly synthesize architectures that also cover: 1NN classification (vector quantization), multishot queries (with different k), LOOCV cross-validation, and compare favorably to GPU implementations. To the best of our knowledge this is the first attempt to design flexible IP cores for the popular kNN classifier.

References

  1. Bennett, K. P. and Mangasarian, O. L. 1992. Robust linear programming discrimination of two linearly inseparable sets. Optimiz. Methods Softw. 1, 23--34.Google ScholarGoogle ScholarCross RefCross Ref
  2. Breast Cancer Dataset. 2010. archive.ics.uci.edu/ml/datasets/Breast+Cancer+Wisconsin+(Diagnostic).Google ScholarGoogle Scholar
  3. Breast Cancer Dataset. 1992. http://archive.ics.uci.edu/ml/datasets/Breast+Cancer+Wisconsin+%28 Original%29.Google ScholarGoogle Scholar
  4. Cappello, P., Davidson, G., Gersho, A., Koc, C., and Somayazulu, V. 1986. A systolic vector quantization processor for real-time speech coding. In Proceedings of the IEEE International Conference on Acoustic, Speech and Signal Processing. 2143--2146.Google ScholarGoogle Scholar
  5. Chen, Y. A., Lin, Y. L., and Chang, L. W. 1992. A systolic algorithm for the k - nearest neighbors problem. IEEE Trans. Comput. 41, 103--108. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Core Generator Tool. 2008. Xilinx user guide. http://www.xilinx.com/itp/xilinx6/books/docs/cgn/cgn.pdf.Google ScholarGoogle Scholar
  7. Duda, R. O., Hart, P. E., and Stork, D. G. 2000. Pattern Classification. Wiley-Interscience. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Garcia, V., Debreuve, E., and Barlaud, M. 2008. Fast k nearest neighbor search using gpu. In Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops. 1--6.Google ScholarGoogle Scholar
  9. Jones, H. D., Powell, A., Bouganis, C. S., and Cheung, Y. K. P. 2010. GPU versus fpga for high productivity computing. In Proceedings of the International Conference on Field Programmable Logic and Applications. 119--124. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Kestur, S., Davis, D. J., and Williams, O. 2010. BLAS comparison on fpga, cpu and gpu. In Proceedings of the IEEE Annual Symposium on VLSI. 288--293. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Kung, S. Y. 1988. VLSI Array Processors. Prentice Hall. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Kurgan, L. A., Cios, K. J., Tadeusiewicz, R., Ogiela, M., and Goodenday, L. S. 2001. Knowledge discovery approach to automated cardiac spect diagnosis. Artif. Intell. Med. 23, 149--169. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Kwai, D. M. and Parhami, B. 2001. Scalable linear array architecture with data-driven control for ultrahigh speed vector quantization. J. VLSI Signal Process. Syst. 28, 235--243. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Liu, J., Li, B., and Liang, D. 2007. Design and implementation of fpga-based modified bknn classifier. Int. J. Comput. Sci. Netw. Secur. 7, 67--71.Google ScholarGoogle Scholar
  15. Lucas, S. M. 1998. A fast exact parallel implementation of the k-nearest neighbor pattern classifier. In Proceedings of the IEEE World Congress on Computational Intelligence. 1867--1872.Google ScholarGoogle Scholar
  16. Mangasarian, O. L., Setiono, R., and Wolberg, W. H. 1990. Pattern recognition via linear programming: Theory and application to medical diagnosis. In Large-Scale Numerical Optimization, T. F. Coleman and Y. Li, Eds., SIAM Publications, Philadelphia, PA, 22--30.Google ScholarGoogle Scholar
  17. Manolakos, E. S. and Logaras, E. 2007. High throughput systolic som ip core for fpgas. In Proceedings of the IEEE International Conference on Acoustic, Speech and Signal Processing. II-61-II-64.Google ScholarGoogle Scholar
  18. Manolakos, E. S. and Stamoulias, I. 2010. IP-cores design for the knn classifier. In Proceedings of the IEEE International Symposium on Circuits and Systems. 4133--4136.Google ScholarGoogle Scholar
  19. Spectf. 2010. Heart dataset. http://archive.ics.uci.edu/ml/datasets/SPECTF+Heart.Google ScholarGoogle Scholar
  20. Stokes, L. M. 2007. A brief look at fpgas, gpus and cell processors. Int. Test Eval. Assoc. J. 28, 2, 9--11.Google ScholarGoogle Scholar
  21. Tahir, M. A. and Bouridane, A. 2006. An fpga based coprocessor for cancer classification using nearest neighbor classifier. In Proceedings of the IEEE International Conference on Acoustic, Speech and Signal Processing.Google ScholarGoogle Scholar
  22. Tahir, M. A., Bouridane, A., Kurugollu, F., and Amira, A. 2005. A novel prostate cancer classification technique using intermediate memory tabu search. EURASIP J. Appl. Signal Process. 14, 2241--2249. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Thomas, D. B., Howes, L., and Luk, W. 2009. A comparison of cpus, gpus, fpgas, and massively parallel processor arrays for random number generation. In Proceeding of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays. 63--72. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Wolberg, W. H. and Mangasarian, O. L. 1990. Multisurface method of pattern separation for medical diagnosis applied to breast cytology. Proc. Nat. Acad. Sci. 9193--9196.Google ScholarGoogle Scholar
  25. Xilinx Power Tools Tutorial. 2010. http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ug733.pdf.Google ScholarGoogle Scholar
  26. Xst. 2008. User guide 10.1. www.xilinx.com.Google ScholarGoogle Scholar
  27. Yeh, Y. J., Li, H. Y., Hwang, W. J., and Fang, C. Y. 2007. FPGA implementation of k-nn classifier based on wavelet transform and partial distance. In Proceedings of the Scandinavian Conference on Image Analysis. 512--521. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Parallel architectures for the kNN classifier -- design of soft IP cores and FPGA implementations

        Recommendations

        Comments

        Login options

        Check if you have access through your login credentials or your institution to get full access on this article.

        Sign in

        Full Access

        PDF Format

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader
        About Cookies On This Site

        We use cookies to ensure that we give you the best experience on our website.

        Learn more

        Got it!