Static analysis of worst-case stack cache behavior

ABSTRACT

Utilizing a stack cache in a real-time system can aid predictability by avoiding interference that heap memory traffic causes on the data cache. While loads and stores are guaranteed cache hits, explicit operations are responsible for managing the stack cache. The behavior of these operations can be analyzed statically. We present algorithms that derive worst-case bounds on the latency-inducing operations of the stack cache. Their results can be used by a static WCET tool. By breaking the analysis down into subproblems that solve intra-procedural data-flow analysis and path searches on the call-graph, the worst-case bounds can be efficiently yet precisely determined. Our evaluation using the MiBench benchmark suite shows that only 37% and 21% of potential stack cache operations actually store to and load from memory, respectively. Analysis times are modest, on average running between 0.46s and 1.30s per benchmark, depending on the size of the stack cache.

References

1. S. Abbaspour, F. Brandner, and M. Schoeberl. A time-predictable stack cache. In Proceedings of the Workshop on Software Technologies for Embedded and Ubiquitous Systems, SEUS '13, 2013.
2. A. V. Aho, M. S. Lam, R. Sethi, and J. D. Ullman. Compilers: Principles, Techniques, and Tools. Addison-Wesley, 2nd edition, 2006.
3. T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein. Introduction to Algorithms. MIT Press, 3rd edition, 2009.
4. C. Cullmann, C. Ferdinand, G. Gebhard, D. Grund, C. Maiza, J. Reineke, B. Triquet, S. Wegener, and R. Wilhelm. Predictability considerations in the design of multi-core embedded systems. Ingénieurs de l'Automobile, 807:36--42, September 2010.
5. C. Ferdinand, R. Heckmann, and B. Franzen. Static memory and timing analysis of embedded systems code. In Proceedings of Symposium on Verification and Validation of Software Systems, VVSS '07, pages 153--163. Eindhoven University of Technology, 2007.
6. C. Ferdinand and R. Wilhelm. Efficient and precise cache behavior prediction for real-time systems. Real-Time Systems, 17(2--3):131--181, 1999.
7. M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. MiBench: A free, commercially representative embedded benchmark suite. In Proceedings of the Workshop on Workload Characterization, 2001.
8. U. Khedker, A. Sanyal, and B. Karkare. Data Flow Analysis: Theory and Practice. CRC Press, Inc., 1st edition, 2009.
9. Y.-T. S. Li and S. Malik. Performance analysis of embedded software using implicit path enumeration. In Proceedings of the Design Automation Conference, DAC '95, pages 456--461. ACM, 1995.
10. P. P. Puschner and A. V. Schedl. Computing maximum task execution times - a graph-based approach. Real-Time Systems, 13(1):67--91, July 1997.
11. M. Schoeberl, B. Huber, and W. Puffitsch. Data cache organization for accurate timing analysis. Real-Time Systems, 49(1):1--28, Jan. 2013.
12. M. Schoeberl, P. Schleuniger, W. Puffitsch, F. Brandner, C. W. Probst, S. Karlsson, and T. Thorn. Towards a time-predictable dual-issue microprocessor: The Patmos approach. In Workshop on Bringing Theory to Practice: Predictability and Performance in Embedded Systems, PPES '11, pages 11--20, 2011.
13. BoundT time and stack analyzer - application note SPARC/ERC32 V7, V8, V8E. Technical Report TR-AN-SPARC-001, Version 7, Tidorum Ltd., 2010.
14. R. T. White, C. A. Healy, D. B. Whalley, F. Mueller, and M. G. Harmon. Timing analysis for data caches and set-associative caches. In Proceedings of the Real-Time Technology and Applications Symposium, RTAS '97, pages 192--203. IEEE, 1997.

Index Terms

• Computer systems organization

  • Embedded and cyber-physical systems

  • Real-time systems

• Theory of computation

  • Semantics and reasoning

    • Program reasoning

      • Program analysis

    • Program semantics