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Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms

Published:01 October 2013Publication History
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Abstract

In FPGA CAD flow, the clustering stage builds the foundation for placement and routing stages and affects performance parameters, such as routability, delay, and channel width significantly. Net sharing and criticality are the two most commonly used factors in clustering cost functions. With this study, we first derive a third term, net-length factor, and then design a generic method for integrating net length into the clustering algorithms. Net-length factor enables characterizing the nets based on the routing stress they might cause during later stages of the CAD flow and is essential for enhancing the routability of the design. We evaluate the effectiveness of integrating net length as a factor into the well-known timing (T-VPack)-, depopulation (T-NDPack)-, and routability (iRAC and T-RPack)-driven clustering algorithms. Through exhaustive experimental studies, we show that net-length factor consistently helps improve the channel-width performance of routability-, depopulation-, and timing-driven clustering algorithms that do not explicitly target low fan-out nets in their cost functions. Particularly, net-length factor leads to average reduction in channel width for T-VPack, T-RPack, and T-NDPack by 11.6%, 10.8%, and 14.2%, respectively, and in a majority of the cases, improves the critical-path delay without increasing the array size.

References

  1. Balachandran, S. and Bhatia, D. 2005. A priori wirelength and interconnect estimation based on circuit characteristic. IEEE Trans. CAD Integr. Circuits Syst. 24, 7, 1054--1065. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Betz, V. and Rose, J. 1997. VPR: A new packing, placement and routing tool for FPGA research. In Proceedings of the 7th International Workshop on Field-Programmable Logic (FPL’97). 213--222. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Betz, V., Rose, J., and Marquardt, A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, Norwell, MA. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Bodapati, S. and Najm, F. N. 2000. Pre-layout estimation of individual wire lengths. In Proceedings of the ACM International Workshop on System-Level Interconnect Prediction (SLIP’00). ACM, New York, NY, 93--98. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Bozorgzadeh, E., Memik, S., Yang, X., and Sarrafzadeh, M. 2004. Routability driven packing: Metrics and algorithms for cluster-based FPGAs. Circuits, Syst. Comput. 13, 1, 77--100.Google ScholarGoogle Scholar
  6. Brown, S., Rose, J., and Vranesic, Z. 1993. A stochastic model to predict the routability of field-programmable gate arrays. IEEE Trans. Comput.-Aid. Design Integr. Circuits Syst. 12, 12, 1827--1838. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Caldwell, A., Kahng, A., and Markov, I. 2000. Can recursive bisection alone produce routable placements? In Proceedings of the 37th Annual Design Automation Conference (DAC’00). ACM, New York, NY, 477--482. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Chen, G. and Cong, J. 2004. Simultaneous timing driven clustering and placement for FPGAs. In Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL’04). 158--167.Google ScholarGoogle Scholar
  9. Chen, D., Vorwerk, K., and Kennings, A. 2007. Improving timing-driven FPGA packing with physical information. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’07). IEEE, Los Alamitos, CA, 117--123.Google ScholarGoogle Scholar
  10. Chen, D., Cong, J., Dong, C., He, L., Li, F., and Peng, C. 2010. Technology mapping and clustering for FPGA architectures with dual supply voltages. IEEE Trans. Comput.-Aid. Design Integr. Circuits Syst. 29, 11, 1709--1722. :http://dx.doi.org/10.1109/TCAD.2010.2061770. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Cheng, C. E. 1994. RISA: Accurate and efficient placement routability modeling. In Proceedings of the International Conference on Computer Aided Design (ICCAD‘94). IEEE Computer Society, Los Alamitos, CA, 690--695. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Cong, J. and Lim, S. 2000. Edge separability based circuit clustering with application to circuit partitioning. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC’00). ACM, New York, NY, 429--434. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Das, J., Wilton, S. J. E., Leong, P., and Luk, W. 2009. Modeling post-techmapping and post-clustering FPGA circuit depth. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’09). IEEE, Los Alamitos, CA, 205--211.Google ScholarGoogle Scholar
  14. Dehon, A. 1996. Reconfigurable architectures for general-purpose computing. Tech. rep. AITR-1586, MIT Artificial Intelligence Laboratory, Cambridge, MA. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Dehon, A. 1999. Balancing inter-connect and computation in a reconfigurable computing array (or, why you don’t really want 100% LUT utilization). In Proceedings of the ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays (FPGA’99). ACM, New York, NY, 69--78. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Dickin, D. and Shannon, L. 2011. Exploring FPGA technology mapping for fracturable LUT minimization. In Proceedings of the IEEE International Conference of Field Programmable Technology (FPT’11). 1--8.Google ScholarGoogle Scholar
  17. Donath, W. 1979. Placement and average interconnection lengths of computer logic. IEEE Trans. Circuits Syst. 26, 4, 272--277.Google ScholarGoogle ScholarCross RefCross Ref
  18. Easwaran, L. and Akoglu, A. 2011. Net-length-based area and routability driven power aware clustering. ACM Trans. Reconfig. Technol. Syst. 4, 4, Article 38. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. El Gamal, A. 1981. A two-dimensional stochastic model for interconnections in master slice integrated circuits. IEEE Trans. Circuits Syst. 28, 2, 127--138.Google ScholarGoogle ScholarCross RefCross Ref
  20. Fang, W. and Rose, J. 2008. Modeling routing demand for early-stage FPGA architecture development. In Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays (FPGA’08). ACM, New York, NY, 139--148. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Hauck, S. and Borriello, G. 1997. IEEE Trans. Comput.-Aid. Design Integr. Circuits Syst. 16, 8, 849--866. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Heineken, H. and Maly, W. 1996. Standard cell interconnect length prediction from structural circuit attributes. In Proceedings of the Custom Integrated Circuits Conference. IEEE, Los Alamitos, CA, 167--170.Google ScholarGoogle Scholar
  23. Hu, B. and Marek-Sadowska, M. 2003. Wire length prediction based clustering and its application in placement. In Proceedings of the 40th Annual Design Automation Conference (DAC’03). ACM, New York, NY, 800--805. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Kahng, A. and Reda, S. 2005. Intrinsic shortest path length: A new, accurate apriori wire-length estimator. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD’05). IEEE Computer Society, Los Alamitos, CA, 173--180. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Kannan, P. and Bhatia, D. 2004. Estimating pre-placement FPGA interconnection requirements. In Proceedings of the 17th International Conference on VLSI Design (VLSID’04). IEEE Computer Society, Los Alamitos, CA, 869--874. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Kravets, V. and Kudva, P. 2003. Understanding metrics in logic synthesis for routability enhancement. In Proceedings of the International Workshop on System-Level Interconnect Prediction (SLIP’03). ACM, New York, NY, 3--5. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. Kudva, P., Sullivan, A., and Dougherty, W. 2002. Metrics for structural logic synthesis. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD’02). ACM, New York, NY, 551--556. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Lamoureux, J. and Wilton, S. J. E. 2003. On the interaction between power-aware FPGA CAD algorithms. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD’03). IEEE Computer Society, Los Alamitos, CA, 701--708. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Landman, S. and Russo, R. L. 1971. On a pin versus block relationship for partitions of logic graphs. IEEE Trans. Comput. 20, 12, 1469--1479. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Li, W. and Banerji, D. K. 1999. Routability prediction for hierarchical FPGAs. In Proceedings of the 9th Great Lakes Symposium on VLSI (GLS’99). IEEE Computer Society, Los Alamitos, CA, 256--259. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. Lin, J., Chen, D., and Cong, J. 2006. Optimal simultaneous mapping and clustering for FPGA delay optimization. In Proceedings of the 43rd Annual Design Automation Conference (DAC’06). ACM, New York, NY, 472--477. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. Liu, H. and Akoglu, A. 2010. Timing-driven non uniform depopulation-based clustering. Int. J. Reconfig. Comput., Article 3. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. Liu, Q. and Marek-Sadowska, M. 2004. Pre-layout wire length and congestion estimation. In Proceedings of the Design Automation Conference (DAC’04). ACM, New York, NY, 582--587. Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. Liu, Q. and Marek-Sadowska, M. 2005. Pre-layout physical connectivity prediction with application in clustering-based placement. In Proceedings of the International Conference on Computer Design (ICCD’05). IEEE Computer Society, Los Alamitos, CA, 31--37. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. Liu, Q., Hu, B., and Marek-Sadowska, M. 2003. Wire length prediction in constraint driven placement. In Proceedings of the International Workshop on System-Level Interconnect Prediction (SLIP’03). ACM, New York, NY, 99--105. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. Liu, Q., Hu, B., and Marek-Sadowska., M. 2004. Individual wire-length prediction with application to timing-driven placement. IEEE Trans. VLSI Syst. 12, 10, 1004--1014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. Liu, Y., Jiang, X., Sun, S., and Wang, G. 2009. An efficient FPGA packing algorithm based on simple dual-output basic logic elements. In Proceedings of the IEEE 8th International Conference on ASIC (ASICON’09). IEEE Press, Los Alamitos, CA, 690--693. :http://dx.doi.org/10.1109/ASICON.2009.5351300.Google ScholarGoogle Scholar
  38. Luu, J., Anderson, J. H., and Rose, J. 2011. Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. In Proceedings of the 19th ACM International Symposium on FPGAs (FPGA’11). 227--236. Google ScholarGoogle ScholarDigital LibraryDigital Library
  39. Mak, T., Sedcole, P., Cheung, P. Y. K., and Luk, W. 2008. Interconnection lengths and delays estimation for communication links in FPGAs. In Proceedings of the International Workshop on System-Level Interconnect Prediction (SLIP’08). ACM, New York, NY, 1--10. Google ScholarGoogle ScholarDigital LibraryDigital Library
  40. Manohararajah, V., Chiu, G. R., Singh, D. P., and Brown, S. D. 2006. Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. In Proceedings of the International Workshop on System-Level Interconnect Prediction (SLIP’06). ACM, New York, NY, 3--8. Google ScholarGoogle ScholarDigital LibraryDigital Library
  41. Manohararajah, V., Chiu, G. R., Singh, D. P., and Brown, S. D. 2007. Predicting interconnect delay for physical synthesis in a FPGA CAD flow. IEEE Trans. VLSI Syst. 15, 8, 895--903. Google ScholarGoogle ScholarDigital LibraryDigital Library
  42. Marquardt, A., Betz, V., and Rose, J. 1999. Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density. In Proceedings of the ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays (FPGA’99). ACM, New York, NY, 37--46. Google ScholarGoogle ScholarDigital LibraryDigital Library
  43. Marquardt, A., Betz, V., and Rose, J. 2000. Speed and area tradeoffs in cluster-based FPGA architectures. IEEE Trans. VLSI Syst. 8, 1, 84--93. Google ScholarGoogle ScholarDigital LibraryDigital Library
  44. Marrakchi, Z., Mrabet, H., and Mehrez, H. 2005. Hierarchical FPGA clustering to improve routability. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE, Los Alamitos, CA, 22--25.Google ScholarGoogle Scholar
  45. Pandit, A. and Akoglu, A. 2007a. Net length based routability driven packing. In Proceedings of the IEEE International Conference on Field-Programmable Technology (ICFPT’07). IEEE, Los Alamitos, CA, 225--232.Google ScholarGoogle Scholar
  46. Pandit, A. and Akoglu, A. 2007b. Wirelength prediction for FPGAs. In Proceedings of 17th International Conference on Field Programmable Logic and Applications. (FPL’07). IEEE, Los Alamitos, CA, 749--752.Google ScholarGoogle Scholar
  47. Pandit, A., Easwaran, L., and Akoglu, A. 2008. Concurrent timing based and routability driven depopulation technique for FPGA packing. In Proceedings of the IEEE International Conference on Field Programmable Technology (ICFPT’08). IEEE, Los Alamitos, CA, 325--328.Google ScholarGoogle Scholar
  48. Rajavel, S. T. and Akoglu, A. 2011. MO-Pack: Many-objective clustering for FPGA CAD. In Proceedings of the ACM/EDAC/IEEE Design Automation Conference (DAC). 818--823. Google ScholarGoogle ScholarDigital LibraryDigital Library
  49. Rose, J., Luu, J., Kent, K., Yu, C. W., Anderson, J. H., Densmore, O., and Jamieson, P. 2012. The VTR project: Architecture and CAD for FPGAs from Verilog to routing. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA’12). Google ScholarGoogle ScholarDigital LibraryDigital Library
  50. Shin, H. and Kim, C. 1993. A simple yet effective technique for partitioning. IEEE Trans. VLSI Syst. 1, 3, 380--386. Google ScholarGoogle ScholarDigital LibraryDigital Library
  51. Singh, A. and Marek-Sadowska, M. 2002. Efficient circuit clustering for area and power reduction in FPGAs. In Proceedings of the ACM/SIGDA 10th International Symposium on Field-Programmable Gate Arrays (FPGA’02). ACM, New York, NY, 59--66. Google ScholarGoogle ScholarDigital LibraryDigital Library
  52. Smith, A., Das, J., and Wilton, S. 2009. Wirelength modeling for homogeneous and heterogeneous FPGA architectural development. In Proceeding of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA’09). ACM, New York, NY, 181--190. Google ScholarGoogle ScholarDigital LibraryDigital Library
  53. Strooband, D., Van Marck, H., and Campenhout, J. V. 1996. An accurate interconnection length estimation for computer logic. In Proceedings of the 6th Great Lakes Symposium on VLSI. 50--55. Google ScholarGoogle ScholarDigital LibraryDigital Library
  54. Swartz, J., Betz, V., and Rose, J. 1998. A fast routability-driven router for FPGAs. In Proceedings of the ACM/SIGDA 6th International Symposium on Field Programmable Gate Arrays (FPGA’98). ACM, New York, NY, 140--149. Google ScholarGoogle ScholarDigital LibraryDigital Library
  55. Tessier, R. and Giza, H. 2000. Balancing logic utilization and area efficiency in FPGAs. In Proceedings of the International Workshop on Field Programmable Logic and Applications (FPL’00). 535--544. Google ScholarGoogle ScholarDigital LibraryDigital Library
  56. Tom, M., Leong, D., and Lemieux, G. 2006. Un/DoPack: Re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD’06). ACM, New York, NY, 680--687. Google ScholarGoogle ScholarDigital LibraryDigital Library
  57. Van Marck, H., Stroobandt, D., and Campenhout, J. V. 1995. Towards an extension of Rent’s rule for describing local variations in interconnection complexity. In Proceedings of 4th International Conference for Young Computer Scientists. Peking University Press, Beijing, 136--141.Google ScholarGoogle Scholar
  58. Wirelength. 2007. http://www.ece.arizona.edu/~rcl/wirelength.html.Google ScholarGoogle Scholar
  59. Wong, J. L., Davoodi, A., Khandelwal, V., Srivastava, A., and Potkonjak, M. 2006. A statistical methodology for wire-length prediction. IEEE Trans. Comput.-Aid. Design Integr. Circuits Syst. 25, 7, 1327--1336. Google ScholarGoogle ScholarDigital LibraryDigital Library
  60. Yang, S. 1991. Logic synthesis and optimization benchmarks, version 3.0. Tech. rep., Microelectronics Center of North Carolina, NC.Google ScholarGoogle Scholar
  61. Yeager, D., Chiu, D., and Lemieux, G. 2007. Congestion estimation and localization in FPGAs: A visual tool for interconnect prediction. In Proceedings of the International Workshop on System Level Interconnect Prediction (SLIP’07). ACM, New York, NY, 33--40. Google ScholarGoogle ScholarDigital LibraryDigital Library

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  1. Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms

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    • Published in

      cover image ACM Transactions on Reconfigurable Technology and Systems
      ACM Transactions on Reconfigurable Technology and Systems  Volume 6, Issue 3
      October 2013
      85 pages
      ISSN:1936-7406
      EISSN:1936-7414
      DOI:10.1145/2535556
      Issue’s Table of Contents

      Copyright © 2013 ACM

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 1 October 2013
      • Accepted: 1 March 2013
      • Revised: 1 November 2012
      • Received: 1 May 2011
      Published in trets Volume 6, Issue 3

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