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FastLane: improving performance of software transactional memory for low thread counts

Published:23 February 2013Publication History
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Abstract

Software transactional memory (STM) can lead to scalable implementations of concurrent programs, as the relative performance of an application increases with the number of threads that support it. However, the absolute performance is typically impaired by the overheads of transaction management and instrumented accesses to shared memory. This often leads STM-based programs with low thread counts to perform worse than a sequential, non-instrumented version of the same application.

In this paper, we propose FastLane, a new STM algorithm that bridges the performance gap between sequential execution and classical STM algorithms when running on few cores. FastLane seeks to reduce instrumentation costs and thus performance degradation in its target operation range. We introduce a novel algorithm that differentiates between two types of threads: One thread (the master) executes transactions pessimistically without ever aborting, thus with minimal instrumentation and management costs, while other threads (the helpers) can commit speculative transactions only when they do not conflict with the master. Helpers thus contribute to the application progress without impairing on the performance of the master.

We implement FastLane as an extension of a state-of-the-art STM runtime system and compiler. Multiple code paths are produced for execution on a single, few, and many cores. The runtime system selects the code path providing the best throughput, depending on the number of cores available on the target machine. Evaluation results indicate that our approach provides promising performance at low thread counts: FastLane almost systematically wins over a classical STM in the 1-6 threads range, and often performs better than sequential execution of the non-instrumented version of the same application starting with 2 threads.

References

  1. G. Blake, R. G. Dreslinski, T. Mudge, and K. Flautner. Evolution of thread-level parallelism in desktop applications. SIGARCH Comput. Archit. News, 38 (3): 302--313, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. D. Christie, J.-W. Chung, S. Diestelhorst, M. Hohmuth, M. Pohlack, C. Fetzer, M. Nowack, T. Riegel, P. Felber, P. Marlier, and E. Riviere. Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack. In Eurosys, Apr. 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. C. Cortes, D. Pregibon, and C. Volinsky. Communities of interest. In Advances in Intelligent Data Analysis, IDA. Springer, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Dalessandro, Dice, Scott, Shavit, and Spear}Dalessandro2010aL. Dalessandro, D. Dice, M. Scott, N. Shavit, and M. Spear. Transactional mutex locks. In Euro-Par, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. L. Dalessandro, M. F. Spear, and M. L. Scott. NOrec: Streamlining STM by abolishing ownership records. In PPoPP, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. D. Dice, O. Shalev, and N. Shavit. Transactional locking II. In DISC, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. A. Dragojević, P. Felber, V. Gramoli, and R. Guerraoui. Why STM can be more than a research toy. CACM, 54 (4): 70--77, Apr. 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. P. Felber, C. Fetzer, and T. Riegel. Dynamic performance tuning of word-based software transactional memory. In PPoPP, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. S. M. Fernandes and J. Cachopo. Lock-free and scalable multi-version software transactional memory. In PPoPP, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. R. Guerraoui and M. Kapalka. On the correctness of transactional memory. In PPoPP, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. T. Harris, J. Larus, and R. Rajwar. Transactional Memory, 2nd edition. Morgan and Claypool Publishers, December 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. C. P. Kruskal, L. Rudolph, and M. Snir. Efficient synchronization of multiprocessors with shared memory. ACM Trans. Program. Lang. Syst., 10 (4): 579--601, Oct. 1988. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. W. Maldonado, P. Marlier, P. Felber, J. Lawall, G. Muller, and E. Riviere. Deadline-aware scheduling for software transactional memory. In DSN, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. A. Matveev and N. Shavit. Towards a fully pessimistic STM model. In TRANSACT, New Orleand, LA, USA, 2012.Google ScholarGoogle Scholar
  15. M. Mehrara, J. Hao, P.-C. Hsu, and S. Mahlke. Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory. In PLDI, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. J. M. Mellor-Crummey and M. L. Scott. Algorithms for scalable synchronization on shared-memory multiprocessors. ACM Trans. Comput. Syst., 9 (1): 21--65, Feb. 1991. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. C. C. Minh, J.-W. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford transactional applications for multi-processing. In IISWC, 2008.Google ScholarGoogle Scholar
  18. C. E. Oancea, A. Mycroft, and T. Harris. A lightweight in-place implementation for software thread-level speculation. In SPAA, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. T. Riegel, P. Felber, and C. Fetzer. A lazy snapshot algorithm with eager validation. In DISC, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. T. Riegel, C. Fetzer, and P. Felber. Automatic data partitioning in software transactional memories. In SPAA, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. A. Roy, S. Hand, and T. Harris. A runtime system for software lock elision. In EuroSys, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. M. F. Spear. Lightweight, robust adaptivity for software transactional memory. In SPAA, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. M. F. Spear, L. Dalessandro, V. J. Marathe, and M. L. Scott. A comprehensive strategy for contention management in software transactional memory. In PPoPP, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. M. F. Spear, K. Kelsey, T. Bai, L. Dalessandro, M. L. Scott, C. Ding, and P. Wu. Fastpath speculative parallelization. In LCPC, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. J. Sreeram, R. Cledat, T. Kumar, and S. Pande. RSTM: A relaxed consistency software trans. memory for multicores. In PACT, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. T. Usui, R. Behrends, J. Evans, and Y. Smaragdakis. Adaptive locks: Combining transactions and locks for efficient concurrency. In PACT, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. J.-T. Wamhoff, T. Riegel, C. Fetzer, and P. Felber. RobuSTM: a robust software transactional memory. In SSS, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. C. Wang, W.-Y. Chen, Y. Wu, B. Saha, and A.-R. Adl-Tabatabai. Code generation and optimization for transactional memory constructs in an unmanaged language. In CGO, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. S. Weigert, M. Hiltunen, and C. Fetzer. Community-based analysis of netflow for early detection of security incidents. In LISA, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library

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      • Published in

        cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 48, Issue 8
        PPoPP '13
        August 2013
        309 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/2517327
        Issue’s Table of Contents
        • cover image ACM Conferences
          PPoPP '13: Proceedings of the 18th ACM SIGPLAN symposium on Principles and practice of parallel programming
          February 2013
          332 pages
          ISBN:9781450319225
          DOI:10.1145/2442516

        Copyright © 2013 ACM

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        Association for Computing Machinery

        New York, NY, United States

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        • Published: 23 February 2013

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