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Programming with hardware lock elision

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Published:23 February 2013Publication History
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Abstract

We present a simple yet effective technique for improving performance of lock-based code using the hardware lock elision (HLE) feature in Intel's upcoming Haswell processor.

We also describe how to extend Haswell's HLE mechanism to achieve a similar effect to our lock elision scheme entirely in hardware.

References

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  4. P. S. Magnusson, A. Landin, and E. Hagersten. Queue locks on cache coherent multiprocessors. In Proceedings of the 8th International Symposium on Parallel Processing, pages 165--171, Washington, DC, USA, 1994. IEEE Computer Society. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. J. M. Mellor-Crummey and M. L. Scott. Algorithms for scalable synchronization on shared-memory multiprocessors. ACM Transactions on Computer Systems, 9(1):21--65, Feb. 1991. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. N. Piggin. x86: FIFO ticket spinlocks. http://lkml.org/lkml/2007/11/1/125, 2007.Google ScholarGoogle Scholar
  7. R. Rajwar and J. R. Goodman. Speculative Lock Elision: enabling highly concurrent multithreaded execution. In MICRO 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library

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      • Published in

        cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 48, Issue 8
        PPoPP '13
        August 2013
        309 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/2517327
        Issue’s Table of Contents
        • cover image ACM Conferences
          PPoPP '13: Proceedings of the 18th ACM SIGPLAN symposium on Principles and practice of parallel programming
          February 2013
          332 pages
          ISBN:9781450319225
          DOI:10.1145/2442516

        Copyright © 2013 Authors

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 23 February 2013

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