skip to main content
research-article

Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system

Published:01 April 2014Publication History
Skip Abstract Section

Abstract

We describe and evaluate explicit reservation of cache memory to reduce the cache-related preemption delay (CRPD) observed when tasks share a cache in a preemptive multitasking hard real-time system. We demonstrate the approach using measurements obtained from a hardware prototype, and present schedulability analyses for systems that share a cache by explicit reservation. These analyses form the basis for a series of experiments to further evaluate the approach. We find that explicit reservation is most useful for larger task sets with high utilization. Some task sets cannot be scheduled with a conventional cache, but are schedulable with explicit reservation.

References

  1. Sebastian Altmeyer, Robert Davis, and Claire Maiza. 2011. Cache related pre-emption delay aware response time analysis for fixed priority pre-emptive systems. In Proceedings of the IEEE 32nd Real-Time Systems Symposium (RTSS'11). IEEE Computer Society, Los Alamitos, CA, 261--271. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Sebastian Altmeyer, Robert I. Davis, and Claire Maiza. 2012. Improved cache related pre-emption delay aware response time analysis for fixed priority pre-emptive systems. Real-Time Syst. 48, 499--526. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Sebastian Altmeyer and Claire Maiza. 2010. Cache-related preemption delay via useful cache blocks: Survey and redefinition. J. Syst. Arch. 57, 707--719. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. A. Arnaud and I. Puaut. 2006. Dynamic Instruction Cache Locking in Hard Real-Time Systems. In Proceedings of the 14th International Conference on Real-Time and Network Systems (RTNS).Google ScholarGoogle Scholar
  5. N. Audsley, A. Burns, M. Richardson, K. Tindell, and A. Wellings. 1993. Applying new scheduling theory to static priority pre-emptive scheduling. Softw. Engin. J. 8, 5, 284--292.Google ScholarGoogle ScholarCross RefCross Ref
  6. T. P. Baker. 1991. Stack-based scheduling of real-time processes. Real-Time Syst. 3, 1, 67--100. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Enrico Bini and Giorgio C. Buttazzo. 2005. Measuring the performance of schedulability tests. Real-Time Syst. 30, 1--2, 129--154. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Bluespec. 2013. About the Synthesizable Modeling Company. http://www.bluespec.com/about/index.htm.Google ScholarGoogle Scholar
  9. Reinder J. Bril, Johan J. Lukkien, and Wim F. Verhaegh. 2009. Worst-case response time analysis of real-time tasks under fixed-priority scheduling with deferred preemption. Real-Time Syst. 42, 1--3, 63--119. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Alan Burns and Andy Wellings. 2009. Real-Time Systems and Programming Languages: Ada, Real-Time Java and C/Real-Time POSIX 4th Ed. Addison-Wesley Educational Publishers Inc. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. J. V. Busquets-Mataix, J. J. Serrano, R. Ors, P. Gil, and A. Wellings. 1996. Adding instruction cache effect to schedulability analysis of preemptive real-time systems. In Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS'96). IEEE Computer Society, LOS Alamitos, CA, 204--218. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. A. Marti Campoy, A. Perles Ivars, and J. V. Busquets Mataix. 2002. Dynamic use of locking caches In Multitask, Preemptive Real-Time Systems. In Proceedings of the International Federation of Automatic Control.Google ScholarGoogle Scholar
  13. Shannon Cepeda. 2009. What you need to know about prefetching. http://software.intel.com/en-us/blogs/2009/08/24/what-you-need-to-know-about-prefetching.Google ScholarGoogle Scholar
  14. Robert Davis, Alan Burns, Reinder J. Bril, and Johan J. Lukkien. 2007. Controller area network (can) schedulability analysis: Refuted, revisited and revised. Real-Time Syst. 35, 3, 239--272. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. R. Davis, A. Zabos, and A. Burns. 2008. Efficient exact schedulability tests for fixed priority real-time systems. IEEE Trans. Comput. 57, 9, 1261--1276. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Digilent. 2013. Atlys Spartan-6 FPGA Development Board. http://www.digilentinc.com/ATLYS/.Google ScholarGoogle Scholar
  17. Heiko Falk, Sascha Plazar, and Henrik Theiling. 2007. Compile-time decided instruction cache locking using worst-case execution paths. In Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'07). ACM, New York, NY, 143--148. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Jan Gustafsson, Adam Betts, Andreas Ermedahl, and Björn Lisper. 2010. The Mälardalen WCET benchmarks - Past, present and future. In Proceedings of the 10th Workshop on Worst-Case Execution Time Analysis.Google ScholarGoogle Scholar
  19. Reinhold Heckmann, Marc Langenbach, Stephan Thesing, and Reinhard Wilhelm. 2003. The influence of processor architecture on the design and the results of WCET tools. Proc. IEEE 91, 7, 1038--1054.Google ScholarGoogle ScholarCross RefCross Ref
  20. John L. Hennessy and David A. Patterson. 2006. Computer Architecture, A Quantitative Approach. 4th Ed. Morgan, Kaufmann Publishers Inc., San Francisco, CA. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. J. Herter, P. Backes, F. Haupenthal, and J. Reineke. 2011. CAMA: A predictable cache-aware memory allocator. In Proceedings of the 23rd Euromicro Conference on Real-Time Systems. 23--32. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Mark D. Hill. 1988. A Case for direct-mapped caches. Computer 21, 12, 25--40. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. M. D. Hill and A. J. Smith. 1989. Evaluating associativity in CPU caches. IEEE Trans. Comput. 38, 12, 1612--1630. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. David B. Kirk. 1989. SMART (Strategic Memory Allocation for Real-Time) cache design. In Proceedings of the IEEE Real-Time Systems Symposium. 229--237.Google ScholarGoogle ScholarCross RefCross Ref
  25. Chang-Gun Lee, Joosun Hahn, Yang-Min Seo, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, and Chong Sang Kim. 1998. Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. IEEE Trans. Comput. 47, 6, 700--713. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Tiantian Liu, Minming Li, and Chun Jason Xue. 2012. Instruction cache locking for multi-task real-time embedded systems. Real-Time Syst. 48, 2, 166--197. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. W. Lunniss, S. Altmeyer, and R. Davis. 2012. Optimising task layout to increase schedulability via reduced cache related pre-emption delays. In Proceedings of the 20th International Conference on Real-Time and Network Systems (RTNS). Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Frank Mueller. 1995. Compiler support for software-based cache partitioning. In Proceedings of the ACM SIGPLAN 1995 Workshop on Languages, Compilers, & Tools for Real-Time Systems (LCTES'95). ACM, New York, NY, 125--133. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Peter Puschner. 2005. Experiments with WCET-oriented programming and the single-path architecture. In Proceedings of the Workshop on Object-Oriented Real-Time Dependable Systems. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Jan Staschulat, Simon Schliecker, and Rolf Ernst. 2005. Scheduling analysis of real-time systems with precise modeling of cache related preemption delay. In Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS'05). IEEE Computer Society, Los Alamitos, CA, 41--48. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. Yudong Tan and Vincent Mooney. 2007. Timing analysis for preemptive multitasking real-time systems with caches. ACM Trans. Embed. Comput. Syst. 6, 1. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. K. W. Tindell, A. Burns, and A. J. Wellings. 1994. An extendible approach for analyzing fixed priority hard real-time tasks. Real-Time Syst. 6, 2, 133--151. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. John Tse and Alan Jay Smith. 1998. CPU cache prefetching: Timing evaluation of hardware implementations. IEEE Trans. Comput. 47, 5, 509--526. Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. Xavier Vera, Björn Lisper, and Jingling Xue. 2007. Data cache locking for tight timing calculations. Trans. Embed. Comput. Syst. 7, 1, 1--38. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. Jack Whitham and Neil C. Audsley. 2012. Explicit reservation of local memory in a predictable, preemptive multitasking real-time system. In Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium (RTAS'12). IEEE Computer Society, Los Alamitos, CA, 3--12. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. Reinhard Wilhelm, Jakob Engblom, Andreas Ermedahl, Niklas Holsti, Stephan Thesing, David Whalley, Guillem Bernat, Christian Ferdinand, Reinhold Heckmann, Tulika Mitra, Frank Mueller, Isabelle Puaut, Peter Puschner, Jan Staschulat, and Per Stenström. 2008. The worst-case execution-time problem+overview of methods and survey of tools. Trans. Embed. Comput. Syst. 7, 3, 1--53. Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. Reinhard Wilhelm, Daniel Grund, Jan Reineke, Marc Schlickling, Markus Pister, and Christian Ferdinand. 2009. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. IEEE Trans. on CAD of Integrated Circuits and Systems 28, 7, 966--978. Google ScholarGoogle ScholarDigital LibraryDigital Library
  38. Xilinx. 2008. MicroBlaze Processor Reference Guide. Manual UG081.Google ScholarGoogle Scholar
  39. Xilinx. 2012. Spartan-6 FPGA Memory Interface Solutions User Guide (AXI). Manual UG416.Google ScholarGoogle Scholar

Index Terms

  1. Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system

        Recommendations

        Comments

        Login options

        Check if you have access through your login credentials or your institution to get full access on this article.

        Sign in

        Full Access

        PDF Format

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader
        About Cookies On This Site

        We use cookies to ensure that we give you the best experience on our website.

        Learn more

        Got it!