skip to main content
research-article

Hybrid Associative Flash Translation Layer for the Performance Optimization of Chip-Level Parallel Flash Memory

Published:01 November 2013Publication History
Skip Abstract Section

Abstract

Flash memory is used widely in the data storage market, particularly low-price MultiLevel Cell (MLC) flash memory, which has been adopted by large-scale storage systems despite its low performance. To overcome the poor performance of MLC flash memory, a system architecture has been designed to optimize chip-level parallelism. This design increases the size of the page unit and the block unit, thereby simultaneously executing operations on multiple chips. Unfortunately, its Flash Translation Layer (FTL) generates many unused sectors in each page, which leads to unnecessary write operations. Furthermore, it reuses an earlier log block scheme, although it generates many erase operations because of its low space utilization. To solve these problems, we propose a hybrid associative FTL (Hybrid-FTL) to enhance the performance of the chip-level parallel flash memory system. Hybrid-FTL reduces the number of write operations by utilizing all of the unused sectors. Furthermore, it reduces the overall number of erase operations by classifying data as hot, cold, or fragment data. Hybrid-FTL requires less mapping information in the DRAM and in the flash memory compared with previous FTL algorithms.

References

  1. Caulfield, A. M., Grupp, L. M., and Swanson, S. 2009. Gordon: Using flash memory to build fast, power-efficient clusters for data-intensive applications. In Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’09). ACM Press, New York, 217--228. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Chang, L.-P. 2010. A hybrid approach to nand-flash-based solid-state disks. IEEE Trans. Comput. 59, 10, 1337--1349. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Chang, Y.-H. and Kuo, T.-W. 2011. A management strategy for the reliability and performance improvement of mlc-based flash-memory storage systems. IEEE Trans. Comput. 60, 3, 305--320. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Cho, H., Shin, D., and Eom, Y. I. 2009. Kast: K-associative sector translation for nand flash memory in real-time systems. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’09). 507--512. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Chu, Y.-S., Hsieh, J.-W., Chang, Y.-H., and Kuo, T.-W. 2009. A set-based mapping strategy for flash-memory reliability enhancement. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’09). 405--410. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Chung, T.-S., Park, D.-J., Park, S., Lee, D.-H., Lee, S.-W., and Song, H.-J. 2009. A survey of flash translation layer. J. Syst. Archit. 55, 6, 332--343. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Electronics, Micron. 2007. Technical note: NAND flash status register response in cache programming operations. http://www.micron.com/.Google ScholarGoogle Scholar
  8. Electronics, Micron. 2012a. Datasheet: DDR3 sdram. http://www.micron.com/.Google ScholarGoogle Scholar
  9. Electronics, Micron. 2012b. Technical note: NAND flash performance increase. http://www.micron.com/.Google ScholarGoogle Scholar
  10. Electronics, Samsung. 2012c. NAND flash memory k9f1g1u0m data book. http://www.datasheetcatalog.com/samsungelectronic/41/.Google ScholarGoogle Scholar
  11. Electronics, Samsung. 2012d. Nand flash memory k9gag08u0m data book. http://www.datasheetarchive.com/samsung+k9gag08u0m-datasheet.html.Google ScholarGoogle Scholar
  12. Electronics, Samsung. 2012e. Page program addressing for mlc nand application note. http://www.samsung.com/global/business/semiconductor/file/product/NAND_app_note_for_Page_Program_Addressing_MLC_rev0-0.pdf.Google ScholarGoogle Scholar
  13. Gal, E. and Toledo, S. 2005. Algorithms and data structures for flash memories. ACM Comput. Surv. 37, 2, 1--30. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Gupta, A., Kim, Y., and Urgaonkar, B. 2009. Dftl: A flash translation layer employing demand-based selective caching of page-level address mappings. In Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’09). 229--240. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Ha, B., Cho, H., and Eom, Y. I. 2011. A study on the block fragmentation problem of ssd based on nand flash memory. In Proceeding of the 5th International Conference on Ubiiquitous Information Management and Communication (ICUIMC’11). Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Hsieh, J.-W., Kuo, T.-W., and Chang, L.-P. 2006. Efficient identification of hot data for flash memory storage systems. ACM Trans. Storage 2, 1, 22--40. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Hu, Y., Jiang, H., Feng, D., Tian, L., Luo, H., and Zhang, S. 2011. Performance impact and interplay of ssd parallelism through advanced commands, allocation strategy and data granularity. In Proceedings of the International Conference on Supercomputing (ICS’11). 96--107. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Jin, S., Kim, J., Kim, J., Huh, J., and Maeng, S. 2011. Sector log: Fine-grained storage management for solid state drives. In Proceedings of the ACM Symposium on Applied Computing (SAC’11). 360--367. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Jung, D., Kang, J.-U., Jo, H., Kim, J.-S., and Lee, J. 2010. Superblock ftl: A superblock-based flash translation layer with a hybrid address translation scheme. ACM Trans. Embedd. Comput. Syst. 9, 4. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Kim, J., Kim, J. M., Noh, S. H., Min, S. L., and Cho, Y. 2002. A space-efficient flash translation layer for compact flash systems. IEEE Trans. Consumer Electron. 48, 2, 366--375. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Kim, J., Seol, J., and Maeng, S. 2010. Kast: K-associative sector translation for nand flash memory in real-time systems. IEICE Trans. 93-D, 6, 1644--1647.Google ScholarGoogle Scholar
  22. Lee, S., Shin, D., Jin Kim, Y., and Kim, J. 2008. Locality-aware sector translation for nand flash memory-based storage systems. ACM SIGOPS Oper. Syst. 42, 6, 36--42. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Lee, S.-W., Park, D.-J., Chung, T.-S., Lee, D.-H., Park, S., and Song, H.-J. 2007. A log buffer based flash transition layer using fully associative sector translation. ACM Trans. Embedd. Comput. Syst. 6, 3. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Park, C., Cheon, W., Kang, J.-U., Roh, K., Cho, W., and Kim, J.-S. 2008. A reconfigurable ftl (flash translation layer) architecture for nand flash-based applications. ACM Trans. Embedd. Comput. Syst. 7, 4. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Hybrid Associative Flash Translation Layer for the Performance Optimization of Chip-Level Parallel Flash Memory

            Recommendations

            Comments

            Login options

            Check if you have access through your login credentials or your institution to get full access on this article.

            Sign in

            Full Access

            PDF Format

            View or Download as a PDF file.

            PDF

            eReader

            View online with eReader.

            eReader
            About Cookies On This Site

            We use cookies to ensure that we give you the best experience on our website.

            Learn more

            Got it!