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A Reconfigurable Parallel Hardware Implementation of the Self-Tuning Regulator

Published:01 December 2013Publication History
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Abstract

The self-tuning regulator (STR) is a popular adaptive control algorithm. A high-performance computer is required for its implementation due to the heavy online computational burden. To extend STR for more real-time applications, a parallel hardware implementation on a low-cost reconfigurable computer is presented. The hardware was incorporated with multistage matrix multiplication (MMM) and trace technique to enhance the processing speed. This design was deeply pipelined to achieve high throughput. The algorithm was prototyped on a Xilinx field-programmable gate array (FPGA) device with a maximum operating frequency of 210.436 MHz. Application-specific integrated circuit (ASIC) implementation of STR was reported.

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              • Published in

                cover image ACM Transactions on Reconfigurable Technology and Systems
                ACM Transactions on Reconfigurable Technology and Systems  Volume 6, Issue 4
                December 2013
                89 pages
                ISSN:1936-7406
                EISSN:1936-7414
                DOI:10.1145/2558905
                • Editor:
                • Steve Wilton
                Issue’s Table of Contents

                Copyright © 2013 ACM

                Publisher

                Association for Computing Machinery

                New York, NY, United States

                Publication History

                • Published: 1 December 2013
                • Accepted: 1 July 2013
                • Revised: 1 May 2013
                • Received: 1 December 2012
                Published in trets Volume 6, Issue 4

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