Abstract
We consider the problem of synthesizing circuits (from C to Verilog) that are optimized to handle unpredictable latencies of memory operations. Unpredictable memory latencies can occur due to the use of on chip caches, DRAM memory modules, buffers/queues, or multiport memories. Typically, high-level synthesis compilers assume fixed and known memory latencies, and thus are able to schedule the code’s operations efficiently. The operations in the source code are scheduled into states of a state machine whose states will be synthesized to Verilog. The goal is to minimize scheduling length by maximizing the number of operations (and in particular memory operations) that are executed in parallel at the same state. However, with unpredictable latencies, there can be an exponential number of possible orders in which these parallel memory operations can terminate. Thus, in order to minimize the scheduling, we need a different schedule for any such order. This is not practical, and we show a technique of synthesizing a compact state machine that schedules only a small subset of these possible termination orders. Our results show that this compact state machine can improve the execution time compared to a regular scheduling that waits for the termination of all the active memory references in every state.
- Brock, B. and Exerman, M. 2006. Cache latencies of the powerpc mpc7451. Freescale Semiconductor Application Note AN2180.Google Scholar
- Cortadella, J., Kishinevsky, M., and Grundmann, B. 2006. Synthesis of synchronous elastic architectures. In Proceedings of the 43rd Annual Design Automation Conference. ACM, 657--662. Google Scholar
Digital Library
- Del Barrio, A., Molina, M., Mendias, J., Hermida, R., and Memik, S. 2010. Using speculative functional units in high level synthesis. In Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, 1779--1784. Google Scholar
Digital Library
- Devadas, S., Ghosh, A., and Keutzer, K. 1994. Logic Synthesis. McGraw-Hill. Google Scholar
Digital Library
- Gajski, D. 1996. Principles of Digital Design. Prentice-Hall, Inc. Google Scholar
Digital Library
- Ku, D. C. and Micheli, G. D. 1992. Relative scheduling under timing constraints: Algorithms for high level synthesis of digital circuits. IEEE Trans. CAD/ICAS 11, 696--718. Google Scholar
Digital Library
- Lattner, C. and Adve, V. 2002. The LLVM instruction set and compilation strategy. Tech. rep. UIUCDCS-R-2002-2292, University of Illinois at Urbana-Champaign.Google Scholar
- McMahon, F. 1986. The Livermore Fortran kernels: A computer test of the numerical performance range. Tech. rep. UCRL-53746, Lawrence Livermore National Laboratory, Livermore, CA.Google Scholar
- Panda, P. R., Dutt, N., and Nicolau, A. 1998. Incorporating DRAM access modes into high-level synthesis. IEEE Trans. Comput. Aid. Des. Integr. Circuits Syst. 17, 96--109. Google Scholar
Digital Library
- Raghunathan, V., Ravi, S., and Lakshminarayana, G. 2000. Integrating variable-latency components into high-level synthesis. IEEE Trans. Comput. Aid. Des. Integr. Circuits Syst. 19, 10, 1105--1117. Google Scholar
Digital Library
- Walker, R. and Chaudhuri, S. 1995. High-level synthesis: Introduction to the scheduling problem. IEEE Des. Test Comput. 12, 2, 60--69. Google Scholar
Digital Library
Index Terms
Optimizing Wait States in the Synthesis of Memory References with Unpredictable Latencies
Recommendations
Characterizing Memory Write References for Efficient Management of Hybrid PCM and DRAM Memory
MASCOTS '11: Proceedings of the 2011 IEEE 19th Annual International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication SystemsIn order to reduce the energy dissipation in main memory of computer systems, phase change memory (PCM) has emerged as one of the most promising technologies to incorporate into the memory hierarchy. However, PCM has two critical weaknesses to ...
A Novel ReRAM-based Main Memory Structure for Optimizing Access Latency and Reliability
DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017Emerging Resistive Memory (ReRAM) is a promising candidate as the replacement for DRAM because of its low power consumption, high density and high endurance. Due to the unique crossbar structure, ReRAM can be constructed with a very high density. ...
Optimizing Scheduling in Embedded CMP Systems with Phase Change Memory
ICPADS '12: Proceedings of the 2012 IEEE 18th International Conference on Parallel and Distributed SystemsPhase Change Memory (PCM) is emerging as one of the most promising alternative technology to the Dynamic RAM (DRAM) when building large-scale main memory systems. Even though the PCM is easy to scale, it encounters serious endurance problems. Writes are ...






Comments