Abstract
Energy and thermal issues are two important concerns for embedded system design. Diminished energy dissipation leads to a longer battery life, while reduced temperature hotspots decelerate the physical failure mechanisms. The instruction fetch logic associated with register access has a significant contribution towards the total energy consumption. Meanwhile, the register file has also been previously shown to exhibit the highest temperature compared to the rest of the components in an embedded processor. Therefore, the optimization of energy and the resolution of the thermal issue for register accesses are of great significance. In this article, register allocation techniques are studied to simultaneously reduce energy consumption and heat buildup on register accesses for embedded systems. Contrary to prevailing intuition, we observe that optimizing energy and optimizing temperature on register accesses conflict with each other. We introduce a rotator hardware in the instruction decoder to facilitate a balanced solution for the two conflicting objectives. Algorithms for register allocation and refinement are proposed based on the access patterns and the effects of the rotator. Experimental results show that the proposed algorithms obtain notable improvements of energy and peak temperature for embedded applications.
- ARM. 2012. http://www.arm.com/products/processors/cortex-a/cortex-a8.php.Google Scholar
- Bouchez, F., Darte, A., Guillon, C., and Rastello, F. 2006. Register allocation: What does the NP-completeness proof of Chaitin et al. really prove? or revisiting register allocation: Why and how. In Proceedings of the 19th International Workshop on Languages and Compilers for Parallel Computing (LCPC'06). 283--298. Google Scholar
Digital Library
- Briggs, P. 1992. Register allocation via graph coloring. Ph.D. Dissertations, Rice University. http://citeseer.ist.psu.edu/briggs92register.html. Google Scholar
Digital Library
- Chaitin, G. J. 1982. Register allocation and spilling via graph coloring. ACM SIGPLAN Not. 39, 4, 66--74.Google Scholar
Digital Library
- Chaitin, G. J., Auslander, M. A., Chandra, A. K., Cocke, J., Hopkins, M. E., and Markstein, P. W. 1981. Register allocation via coloring. Comput. Lang. 6, 47--57. Google Scholar
Digital Library
- Chang, J. and Pedram, M. 1995. Register allocation and binding for lower power. In Proceedings of the Design Automation Conference (DAC'95). 29--35. Google Scholar
Digital Library
- Chow, F. C. and Hennessy, J. L. 1990. The priority-based register allocation. ACM Trans. Program. Lang. Syst. 12, 4, 501--536. Google Scholar
Digital Library
- Farach, M. and Liberatore, V. 1998. On local register allocation. In Proceedings of the 9th Annual ACM-SIAM Symposium on Discrete Algorithms. 564--573. Google Scholar
Digital Library
- Fu, C. and Wilken, K. 2002. A faster optimal register allocator. In Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture. 245--256. Google Scholar
Digital Library
- Gebotys, C. 1997. Low energy memory and register allocation using network flow. In Proceedings of the International Conference on Design Automation Conference (DAC'97). 435--440. Google Scholar
Digital Library
- Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin, T. M., Mudge, T., and Brown, R. B. 2001. MiBench: A free, commercially representative embedded benchmark suite. In Proceedings of the IEEE International Workshop on Workload Characterization (WWC-4). 3--14. Google Scholar
Digital Library
- Homayoun, H., Gupta, A., Veidenbaum, A. V., Sasan, A., Kurdahi, F. J., and Dutt, N. 2010. Relocate: Register file local access pattern redistribution mechanism for power and thermal management in out-of-order embedded processor. In Proceedings of the International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC). 216--231. Google Scholar
Digital Library
- HotSpot. 2011. http://lava.cs.virginia.edu/HotSpot/.Google Scholar
- Hsieh, W. and Hwang, T. 2009. Thermal-aware post compilation for vliw architectures. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'09). 606--611. Google Scholar
Digital Library
- Huang, Y., Liu, T., and Xue, C. J. 2012. Register allocation for write activity minimization on non-volatile main memory for embedded systems. J. Syst. Architect. Embed. Syst. Design 58, 1, 13--23. Google Scholar
Digital Library
- Koes, D. R. and Goldstein, S. C. 2006. A global progressive register allocator. SIGPLAN Not. 41, 204--215. Google Scholar
Digital Library
- Lasance, C. J. 2003. Thermally driven reliability issues in microelectronic systems: Status-quo and challenges. Microelectron. Reliab. 43, 12, 1969--1974.Google Scholar
Cross Ref
- Martin, M., Roth, A., and Fischer, C. 1997. Exploiting dead value information. In Proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture. 125--135. Google Scholar
Digital Library
- Panda, P. R. and Dutt, N. D. 1999. Low-power memory mapping through reducing address bus activity. IEEE Trans. VLSI Syst. 7, 3, 309--320. Google Scholar
Digital Library
- Patel, K., Lee, W., and Pedram, M. 2007. Active bank switching for temperature control of the register file in a microprocessor. In Proceedings of the 17th ACM Great Lakes Symposium on VLSI. 231--234. Google Scholar
Digital Library
- Pereira, F. M. Q. and Palsberg, J. 2006. Register allocation after classical SSA elimination is NP-complete. Foundations of Software Science and Computation Structures. Lecture Notes in Computer Science, Series, vol. 3921, Springer Verlag, Berlin, 79--93. Google Scholar
Digital Library
- Pereira, F. and Palsberg, J. 2005. Register allocation via coloring of chordal graphs. In Programming Languages and Systems. Lecture Notes in Computer Science, vol. 3780, Springer Verlag, Berlin, 315--329. Google Scholar
Digital Library
- Pereira, F. M. and Palsberg, J. 2008. Register allocation by puzzle solving. SIGPLAN Not. 43, 216--226. Google Scholar
Digital Library
- Petrov, P. and Orailoglu, A. 2003. Compiler-based register name adjustment for low-power embedded processors. In Proceedings of the International Conference on Computer-Aided Design (ICCAD'03). 523--527. Google Scholar
Digital Library
- Rusu, S. and Singer, G. 2000. The first IA-64 microprocessor. IEEE J. Solid-State Circuits 35, 11, 1539--1544.Google Scholar
Cross Ref
- Scholz, B. and Eckstein, E. 2002. Register allocation for irregular architectures. SIGPLAN Not. 37, 139--148. Google Scholar
Digital Library
- SimpleScalar. 2011. http://www.simplescalar.com/.Google Scholar
- Skadron, K., Stan, M., Huang, W., Velusamy, S., Sankaranarayanan, K., and Tarjan, D. 2003. Temperature-aware microarchitecture. In Proceedings of the 30th International Symposium on Computer Architecture (ISCA). 2--12. Google Scholar
Digital Library
- Srinivasan, J. and Adve, S. 2003. Predictive dynamic thermal management for multimedia applications. In Proceedings of the International Conference on Supercomputing (ICS). 109--120. Google Scholar
Digital Library
- Stan, M. R. and Burleson, W. P. 1995. Bus-invert coding for low-power I/O. IEEE Trans. VLSI Syst. 3, 1, 49--58. Google Scholar
Digital Library
- Yang, C. and Orailoglu, A. 2009. Processor reliability enhancement through compiler-directed register file peak temperature reduction. In Proceedings of the 39th Annual IEEE/IFIP International Conference on Dependable Systems and Networks. 468--477.Google Scholar
- Zhang, Y., Hu, X., and Chen, D. Z. 2002. Efficient global register allocation for minimizing energy consumption. ACM SIGPLAN Not. 37, 4, 42--53. Google Scholar
Digital Library
- Zhou, X., Yu, C., and Petrov, P. 2008. Compiler-driven register re-assignment for register file power-density and temperature reduction. In Proceedings of the International Conference on Design Automation Conference (DAC'08). 750--753. Google Scholar
Digital Library
- Zhuang, X. and Pande, S. 2005. Differential register allocation. SIGPLAN Not. 40, 168--179. Google Scholar
Digital Library
Index Terms
Register allocation for embedded systems to simultaneously reduce energy and temperature on registers
Recommendations
Differential register allocation
PLDI '05: Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementationMicro-architecture designers are very cautious about expanding the number of architected registers (also the register field), because increasing the register field adds to the code size, raises I-cache and memory pressure, complicates processor ...
Differential register allocation
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementationMicro-architecture designers are very cautious about expanding the number of architected registers (also the register field), because increasing the register field adds to the code size, raises I-cache and memory pressure, complicates processor ...
Bytewise Register Allocation
SCOPES '15: Proceedings of the 18th International Workshop on Software and Compilers for Embedded SystemsTraditionally, variables have been considered as atoms by register allocation: Each variable was to be placed in one register, or spilt (placed in main memory) or rematerialized (recalculated as needed). Some flexibility arose from what would be ...






Comments