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Maintaining real-time application timing similarity for defect-tolerant NoC-based many-core systems

Published:27 January 2014Publication History
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Abstract

Many-core Network-on-Chip (NoC) processors are emerging in broad application areas, including those with timing requirements, such as real-time and multimedia applications. Typically, these processors employ core-level backup to improve yield. However, when defective cores are replaced by backup ones, the NoC topology changes. Consequently, a fine-tuned application based on timing parameters given by one topology may not meet the expected timing behavior under the new one. We first develop a metric to measure timing similarity of an application on different NoC topologies and then propose mixed binary quadratic programming and greedy algorithms to reconfigure a defect-tolerant many-core NoC.

References

  1. D. Axehill. 2005. Applications of integer quadratic programming in control and communication. Ph.D. dissertation. Department of Electrical Engineering, Köping University.Google ScholarGoogle Scholar
  2. L. Benini and G. De Micheli. 2002. Networks on chips: A new SoC paradigm. IEEE Comput. 35, 1, 70--78. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. T. Bjerregaard and J. Sparso. 2005. A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip. In Proceedings of the IEEE/ACM Design, Automation and Test in Europe Conference (DATE). 1226--1231. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. T. M. Burks and K. Sakallah. 1993. Min-max linear programming and the timing analysis of digital circuits. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 152--155. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. C.-L. Chou and R. Marculescu. 2008. Contention-aware application mapping for Network-On-Chip communication architectures. In Proceedings of the IEEE International Conference on Computer Design (ICCD). 164--169.Google ScholarGoogle Scholar
  6. W. J. Dally and B. Towles. 2001. Route packets, not wires: On-chip interconnection networks. In Proceedings of the 38th Design Automation Conference (DAC). 684--689. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. O. Derin, D. Kabakci, and L. Fiorin. 2011. Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors. In Proceedings of the 5th IEEE/ACM International Symposium on Networks on Chip (NoCS). 129--136. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. R. Dick. 2007. Embedded System Synthesis Benchmarks (E3S). http://ziyang.eecs.umich.edu/dickrp/e3s/.Google ScholarGoogle Scholar
  9. R. P. Dick, D. L. Rhodes, and W. Wolf. 1998. TGFF: Task graphs for free. In Proceedings of the 6th International Workshop on Hardware/Software Codesign (CODES/CASHE). 97--101. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. K. Goossens, J. Dielissen, and A. Radulescu. 2005. AEthereal network on chip: Concepts, architectures, and implementations. IEEE Design Test Comput. 22, 5 (2005), 414--421. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. H. Gu, C. Li, and S. Sun. 2007. Research on mapping algorithm of irregular mesh NoC for portable multimedia appliances. In Proceedings of the IET Conference on Wireless, Mobile and Sensor Networks (CCWMSN). 697--700.Google ScholarGoogle Scholar
  12. T. Hastie, R. Tibshirani, and J. H. Friedman. 2008. The Elements of Statistical Learning: Data Mining, Inference, and Prediction. Springer-Verlag, Berlin.Google ScholarGoogle Scholar
  13. T. Henzinger, R. Majumdar, and V. Prabhu. 2005. Quantifying similarities between timed systems. In Proceedings of the 3rd International Conference on Formal Modeling and Analysis of Timed Systems (FORMATS). 226--241. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. IBM. 2008. IBM ILOG CPLEX Optimizer. http://www-01.ibm.com/software/integration/optimization/cplex-optimizer/.Google ScholarGoogle Scholar
  15. L. Jain, B. M. Al-Hashimi, M. S. Gaur, V. Laxmi, and A. Narayanan. 2007. NIRGAM: A simulator for NoC interconnect routing and application modeling. In Proceedings of the Workshop on Diagnostic Services in Network-on-Chips, Design, Automation and Test in Europe Conference (DATE). 16--20.Google ScholarGoogle Scholar
  16. A. Lankes, A. Herkersdorf, S. Sonntag, and H. Reinig. 2009. NoC topology exploration for mobile multimedia applications. In Proceedings of the 16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS). 707--710.Google ScholarGoogle Scholar
  17. T. Lei and S. Kumar. 2003. A two-step genetic algorithm for mapping task graphs to a network on chip architecture. In Proceedings of the IEEE Euromicro Symposium on Digital System Design. 180--187. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. J. W. S. Liu. 2000. Real-Time Systems 1st. ed. Prentice Hall PTR, Upper Saddle River, NJ.Google ScholarGoogle Scholar
  19. N. Ma, Z. Lu, Z. Pang, and L. Zheng. 2010. System-level exploration of mesh-based NoC architectures for multimedia applications. In Proceedings of the IEEE International SOC Conference (SOCC). 99--104.Google ScholarGoogle Scholar
  20. E. Sperling. 2007. Turn down the heat…please. http://dopu.cs.auc.dk.Google ScholarGoogle Scholar
  21. N. Thakoor and J. Gao. 2011. Branch-and-bound for model selection and its computational complexity. IEEE Trans. Knowl. Data Eng. 23, 5, 655--668. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. L. A. Wolsey. 1998. Integer Programming. Wiley-Interscience, NY.Google ScholarGoogle Scholar
  23. Y. Yu, S. Ren, and O. Frieder. 2010. Feasibility of semiring-based timing constraints. ACM Trans. Embed. Comput. Sys. 9, 4, 33. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. K. Yue, S. Ghalim, Z. Li, F. Lockom, S. Ren, L. Zhang, and X. Li. 2011. A greedy approach to tolerate defect cores for multimedia applications. In Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia). 112--119.Google ScholarGoogle Scholar
  25. L. Zhang, Y. Han, Q. Xu, and X. Li. 2008. Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology. In Proceedings of the IEEE/ACM Design, Automation and Test in Europe Conference (DATE). 891--896. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. L. Zhang, Y. Han, Q. Xu, X. Li, and H. Li. 2009. On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems. IEEE Trans. VLSI Syst. 17, 9, 1173--1186. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. L. Zhang, Y. Yu, J. Dong, Y. Han, S. Ren, and X. Li. 2010. Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors. In Proceedings of the IEEE/ACM Design, Automation Test in Europe Conference (DATE). 1566--1571. Google ScholarGoogle ScholarDigital LibraryDigital Library

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