skip to main content
10.1145/2554688.2554787acmconferencesArticle/Chapter ViewAbstractPublication PagesfpgaConference Proceedingsconference-collections
research-article

Hardware acceleration of database operations

Published:26 February 2014Publication History

ABSTRACT

As the amount of memory in database systems grows, entire database tables, or even databases, are able to fit in the system's memory, making in-memory database operations more prevalent. This shift from disk-based to in-memory database systems has contributed to a move from row-wise to columnar data storage. Furthermore, common database workloads have grown beyond online transaction processing (OLTP) to include online analytical processing and data mining. These workloads analyze huge datasets that are often irregular and not indexed, making traditional database operations like joins much more expensive.

In this paper we explore using dedicated hardware to accelerate in-memory database operations. We present hardware to accelerate the selection process of compacting a single column into a linear column of selected data, joining two sorted columns via merging, and sorting a column. Finally, we put these primitives together to accelerate an entire join operation. We implement a prototype of this system using FPGAs and show substantial improvements in both absolute throughput and utilization of memory bandwidth. Using the prototype as a guide, we explore how the hardware resources required by our design change with the desired throughput.

References

  1. M. Bauer, H. Cook, and B. Khailany. CudaDMA: optimizing GPU memory bandwidth via warp specialization. In High Performance Computing, Networking, Storage and Analysis, SC'11. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. S. Borkar and A. A. Chien. The future of microprocessors. Commun. ACM, 54(5):67--77, May 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De. Parameter variations and impact on circuits and microarchitecture. In Design Automation Conference, June 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. J. Chhugani, A. D. Nguyen, V. W. Lee, W. Macy, M. Hagog, Y.-K. Chen, A. Baransi, S. Kumar, and P. Dubey. Efficient implementation of sorting on multi-core SIMD CPU architecture. Proc. VLDB Endow., August 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. A. A. Chien, A. Snavely, and M. Gahagan. 10x10: A general-purpose architectural approach to heterogeneity and energy efficiency. Procedia Computer Science, 4(0):1987--1996, 2011.Google ScholarGoogle ScholarCross RefCross Ref
  6. T. Kaldewey, G. Lohman, R. Mueller, and P. Volk. GPU join processing revisited. In Workshop on Data Management on New Hardware, DaMoN '12. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. C. Kim, T. Kaldewey, V. W. Lee, E. Sedlar, A. D. Nguyen, N. Satish, J. Chhugani, A. Di Blas, and P. Dubey. Sort vs. hash revisited: fast join implementation on modern multi-core CPUs. Proc. VLDB Endow., August 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. D. Koch and J. Torresen. FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting. In Field Programmable Gate Arrays, FPGA '11. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. N. Leischner, V. Osipov, and P. Sanders. GPU sample sort. In Parallel Distributed Processing, IPDPS '10.Google ScholarGoogle Scholar
  10. J. D. McCalpin. STREAM: Sustainable memory bandwidth in high performance computers. http://www.cs.virginia.edu/stream/.Google ScholarGoogle Scholar
  11. R. Mueller, J. Teubner, and G. Alonso. Glacier: a query-to-hardware compiler. In Conference on Management of data, SIGMOD '10. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. R. Mueller, J. Teubner, and G. Alonso. Data processing on FPGAs. Proc. VLDB Endow., August 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. R. Mueller, J. Teubner, and G. Alonso. Streams on wires: a query compiler for FPGAs. Proc. VLDB Endow., August 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Netezza. The Netezza FAST engines framework.Google ScholarGoogle Scholar
  15. N. Satish, M. Harris, and M. Garland. Designing efficient sorting algorithms for manycore GPUs. In Parallel Distributed Processing, IPDPS '09. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. N. Satish, C. Kim, J. Chhugani, A. D. Nguyen, V. W. Lee, D. Kim, and P. Dubey. Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort. In Conference on Management of data, SIGMOD '10. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. E. Sintorn and U. Assarsson. Fast parallel GPU-sorting using a hybrid algorithm. Journal of Parallel and Distributed Computing, 68(10), 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. B. Sukhwani, H. Min, M. Thoennes, P. Dube, B. Iyer, B. Brezzo, D. Dillenberger, and S. Asaad. Database analytics acceleration using FPGAs. In Parallel Architectures and Compilation Techniques, PACT '12. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Hardware acceleration of database operations

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in
    • Published in

      cover image ACM Conferences
      FPGA '14: Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
      February 2014
      272 pages
      ISBN:9781450326711
      DOI:10.1145/2554688

      Copyright © 2014 ACM

      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 26 February 2014

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • research-article

      Acceptance Rates

      FPGA '14 Paper Acceptance Rate30of110submissions,27%Overall Acceptance Rate125of627submissions,20%

      Upcoming Conference

      FPGA '24

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader