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Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration

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Published:04 July 2014Publication History
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Abstract

This article proposes a reconfigurable Network-on-Chip (NoC) architecture based on mesh topology. It provides a local reconfiguration of cores to connect to any of the neighboring routers, depending upon the currently executing application. The area overhead for this local reconfiguration has been shown to be very small. We have also presented the strategy to map the cores of an application set onto this architecture. This has been achieved via a two-phase procedure. In the first phase, the cores of the combined application set are mapped tentatively to individual routers, minimizing the communication cost. In the second phase, for each application, positions of individual cores are finalized. A core gets attached to any neighbor of its tentative allocation. We have proposed Integer Linear Programming (ILP) formulation of both the phases. Since ILP takes large amount of CPU time, we have also formulated a Particle Swarm Optimization (PSO)-based solution for the two phases. A heuristic approach has also been developed for the reconfiguration. Comparison of communication cost, latency and network energy have been carried out for the applications, before and after reconfiguration. It shows significant improvement in performance via reconfiguration.

References

  1. B. Ahmad, A. T. Erdogan, and S. Khawam. 2006. Architecture of a dynamically reconfigurable NoC for adaptive reconfigurable MPSoC. In Proceedings of the 1st NASA/ESA Conference on Adaptive Hardware and Systems. 405--411. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. D. Atienza, F. Angiolini, S. Murali, A. Pullini, L. Benini, and D. G. Micheli. 2008. Network-on-chip design and synthesis outlook. Integration: VLSI J. 41, 2. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. A. Avakian, J. Nafziger, A. Panda, and R. Vemuri. 2010. A reconfigurable architecture for multicore systems. In Proceedings of the International Symposium on Parallel & Distributed Processing. 1--8.Google ScholarGoogle Scholar
  4. T. A. Bartic, J. Y. Mignolet, T. Nollet Marescaux, D. Verkest, S. Vernalde, and R. Lauwereins. 2005. Topology adaptive network-on-chip design and implementation. IEE Proc.: Comput. Digital Tech. 152, 4, 467--472.Google ScholarGoogle ScholarCross RefCross Ref
  5. T. A. Bartic, J. Y. Mignolet, T. Nollet Marescaux, D. Verkest, S. Vernalde, and R. Lauwereins. 2003. Highly scalable network on chip for reconfigurable systems. In Proceedings of the International Symposium on System-on-Chip. 79--82.Google ScholarGoogle Scholar
  6. L. Benini. 2006. Application specific NoC design. In Proceedings of the Conference on Design, Automation and Test in Europe. 1--5. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. D. Bertozzi, A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou, L. Benini, and Micheli, G. D. 2005. NoC synthesis flow for customized domain specific multiprocessor systems-on-chip. IEEE Trans. Parallel Distrib. Syst. 16, 2, 113--129. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. C. L. Chou, U. Y. Ogras, and R. Marculescu. 2008. Energy- and performance-aware incremental mapping for NoCs with multiple voltage levels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27, 10, 1866--1879. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. CPLEX. 2013. www.ibm.com/software/in/integration/optimization/cplex.Google ScholarGoogle Scholar
  10. W. J. Dally and B. Towles. 2001. Route packets, not wires: On-chip interconnection networks. In Proceedings of Design Automation Conference. 684--689. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Design Vision. 2003. Design Vision User Guide, Version U-2003.03, March 2003, Synopsys, Inc.Google ScholarGoogle Scholar
  12. R. P. Dick, D. L. Rhodes, and W. Wolf. 1998. TGFF: Task graphs for free. In Proceedings of the 6th International Workshop on Hardware/Software Codesign. 97--101. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. H. Ding, H. Gu, B. Li, and K. Du. 2012. Configuring algorithm for reconfigurable network-on-chip architecture. In Proceedings of the International Conference on Consumer Electronics, Communications and Networks. 222--225.Google ScholarGoogle Scholar
  14. V. Dumitriu and G. N. Khan. 2009. Throughput-oriented NoC topology generation and analysis for high performance SoCs. IEEE Trans. VLSI Syst. 17, 10, 1433--1446. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. H. Elmiligi, M. W. El-Kharashi, and F. Gebali. 2007. Introducing OperaNP: A reconfigurable noc-based platform. In Proceedings of the Canadian Conference on Electrical and Computer Engineering. 940--943.Google ScholarGoogle Scholar
  16. L. Guilan, Z. Hai, and S. Chunhe. 2008. Convergence analysis of a dynamic discrete PSO algorithm. In Proceedings of the 1st International Conference on Intelligent Networks and Intelligent Systems. 89--92. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. HSPICE. 2003. HSPICE Reference Guide, U-2003.09, September 2003.Google ScholarGoogle Scholar
  18. J. Hu and R. Marculescu. 2005. Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24, 4, 551--562. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. A. B. Kahng, L. Bin, S. P. Li, and K. Samadi. 2012. ORION 2.0: A power-area simulator for interconnection networks. IEEE Trans. VLSI Syst, 20, 1, 191--196. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. J. Kennedy and R. Eberhart. 1995. Particle swarm optimization. In Proceedings of the IEEE International Conference on Neural Networks. 1942--1948.Google ScholarGoogle Scholar
  21. S. Kundu, J. Soumya, and S. Chattopadhyay. 2012. Design and evaluation of mesh-of-tree based network-on chip using virtual channel router. Microprocess. Microsyst. 36, 6, 471--488. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. S. Kundu and S. Chattopadhyay. 2008. Network-on-chip architecture design based on mesh-of-tree deterministic routing topology. Int. J. High Perform. Syst. Archi. 1, 3. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. K. Kunert, M. Wecksten, and M. Jonsson. 2007. Algorithm for the choice of topology in reconfigurable on-chip networks with real time support. In Proceedings of the 2nd International Conference on Nano-Networks. 13. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. M. Modarressi and H. Sarbazi-Azad. 2007. Power-aware mapping for reconfigurable NoC architectures. In Proceedings of the 25th International Conference on Computer Design. 417--422.Google ScholarGoogle Scholar
  25. M. Modarressi, H. Sarbazi-Azad, and A. Tavakkol. 2010. An efficient dynamically reconfigurable on-chip network architecture. In Proceedings of the Design Automation Conference. 166--169. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. M. Modarressi, A. Tavakkol, and H. Sarbazi-Azad. 2011. Application-aware topology reconfiguration for on-chip networks. IEEE Trans. VLSI Syst. 19, 11, 2010--2022. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. S. Murali and Micheli, G. D. 2004. Bandwidth constrained mapping of cores onto NoC architectures. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. 896--901. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. S. Murali, M. Coenen, A. Radulescu, K. Goossens, and Micheli, G. D. 2006a. A methodology for mapping multiple use-cases onto networks on chips. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. 118--123. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. S. Murali, M. Coenen, A. Radulescu, K. Goossens, and Micheli, G. D. 2006b. Mapping and configuration methods for multi-use-case networks on chips. In Proceedings of the Design Automation, Asia and South Pacific Conference. 24--27. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. U. Y. Ogras and R. Marculescu. 2005. Energy- and performance-driven NoC communication architecture synthesis using a decomposition approach. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. 352--357. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. V. Rana, D. Atienza, M. D. Santambrogio, D. Sciuto, and Micheli, G. D. 2009. A reconfigurable network-on-chip architecture for optimal multi-processor SoC communication. In Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration. 1--20.Google ScholarGoogle Scholar
  32. P. K. Sahu and S. Chattopdhyay. 2013. A survey on application mapping strategies for network-on-chip design. J. Syst. Archit. 59, 1, 50--76. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. P. K. Sahu, T. Shah, K. Manna, and S. Chattopadhyay. 2013. Application mapping onto mesh-based network-on-chip using discrete particle swarm optimization. IEEE Trans. VLSI Syst. DOI: 10.1109/TVLSI.2013.2240708. Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. J. Soumya and S. Chattopadhyay. 2013. Application-specific network-on-chip synthesis with flexible router placement. J. Syst. Archit. 59, 361--371. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. K. Srinivasan, K. S. Chatha, and G. Konjevod. 2006. Linear-programming-based techniques for synthesis of network-on-chip architectures. IEEE Trans. VLSI Syst. 14, 4, 407--420. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. M. B. Stensgaard and J. Sparso. 2008. ReNoC: A network-on-chip architecture with reconfigurable topology. In Proceedings of the 2nd ACM/IEEE International Symposium on Networks-on-Chip. 55--4. Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. S. Tosun. 2011. New heuristic algorithm for energy aware application mapping and routing on mesh-based NoCs. J. Syst. Archit. 57, 69--78. Google ScholarGoogle ScholarDigital LibraryDigital Library
  38. G. V. Varatkar and R. Marculescu. 2004. On-chip traffic modelling and synthesis for MPEG-2 video applications. IEEE Trans. VLSI Syst. 12, 1, 108--119. Google ScholarGoogle ScholarDigital LibraryDigital Library
  39. K. P. Wang, L. Huang, C. G. Zhou, and W. Pang. 2003. Particle swarm optimization for traveling salesman problem. In Proceedings of the International Conference on Machine Learning and Cybernetics. 1583--1585.Google ScholarGoogle Scholar
  40. X. Wang, M. Yang, Y. Jiang, and P. Liu. 2010. Power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints. ACM Trans. Archit. Code Optim. 7, 1, 1--30. Google ScholarGoogle ScholarDigital LibraryDigital Library
  41. L. W. Wu, W. X. Tang, and Y. Hsu. 2011. A novel architecture and routing algorithm for dynamic reconfigurable network-on-chip. In Proceedings of the IEEE 9th International Symposium on Parallel and Distributed Processing with Applications. 177--182. Google ScholarGoogle ScholarDigital LibraryDigital Library
  42. B. Yang, L. Guang, T. Säntti, and J. Plosila. 2013. Mapping multiple applications with unbounded and bounded number of cores on many-core networks-on-chip. Microprocess. Microsyst. 37, 4--5, 460--471.Google ScholarGoogle ScholarCross RefCross Ref
  43. B. Yang, L. Guang, T. C. Xu, T. Säntti, and J. Plosila. 2010. Multi-application mapping algorithm for network-on-chip platforms. In Proceedings of the IEEE 26th Convention of Electrical and Electronics Engineers in Israel. 17--20.Google ScholarGoogle Scholar
  44. L. Zheng, C. Jueping, D. Ming, Y. Lei, and L. Zan. 2010. Hybrid communication reconfigurable network on chip for MPSoC. In Proceedings of the 24th IEEE International Conference on Advanced Information Networking and Applications. 356--361. Google ScholarGoogle ScholarDigital LibraryDigital Library

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