skip to main content
research-article

High-Level Abstractions and Modular Debugging for FPGA Design Validation

Published:01 February 2014Publication History
Skip Abstract Section

Abstract

Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide visibility and control of the different stages of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not allow the design to be run at full speed. Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. The developed approach provides two means of directly validating synthesized hardware designs. The first allows the original high-level model written in C or C++ to be directly coupled to the synthesized hardware, abstracting away the traditional gate-level view of designs. A high-level programmatic interface allows the synthesized design to be validated directly by the software reference model. The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger. This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a running design on an FPGA.

References

  1. Altera Corporation. a. Design debugging using the SignalTap II embedded logic analyzer. http://www.altera.com/literature/hb/qts/qts_qii53009.pdf.Google ScholarGoogle Scholar
  2. Altera Corporation. b. Quartus II incremental compilation for hierarchical and team-based design. http://www.altera.com/literature/hb/qts/qts_qii51015.pdf.Google ScholarGoogle Scholar
  3. ARM Ltd. ARM information center. http://infocenter.arm.com/.Google ScholarGoogle Scholar
  4. Chandrasekharan, A. 2010. Accelerating incremental floorplanning of partially reconfigurable designs to improve FPGA productivity. M.S. thesis, Virginia Polytechnic Institute and State University, Blacksburg, VA.Google ScholarGoogle Scholar
  5. Chandrasekharan, A., Rajagopalan, S., Subbarayan, G., Frangieh, T., Iskander, Y., Craven, S., and Patterson, C. 2010. Accelerating FPGA development through the automatic parallel application of standard implementation tools. In Proceedings of the International Conference on Field-Programmable Technology (FPT). 53--60.Google ScholarGoogle Scholar
  6. Colwell, R. P. 2006. The Pentium Chronicles: The People, Passion, and Politics behind Intel’s Landmark Chips. John Wiley & Sons, Inc., New York. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Craven, S. D. 2008. Structured approach to dynamic computing application development. Ph.D. thesis, Virginia Polytechnic Institute and State University, Blacksburg, VA.Google ScholarGoogle Scholar
  8. de Dinechin, F. and Pasca, B. FloPoCo. http://flopoco.gforge.inria.fr/.Google ScholarGoogle Scholar
  9. EE Times. 2011. FPGA tool vendor GateRocket folds. EE Times. http://www.eetimes.com/electronics-news/4218492/FPGA-tool-vendor-GateRocker-folds.Google ScholarGoogle Scholar
  10. Frangieh, T., Chandrasekharan, A., Rajagopalan, S., Iskander, Y., Craven, S., and Patterson, C. 2010. PATIS: Using partial configuration to improve static FPGA design productivity. In Proceedings of the 17th Reconfigurable Architectures Workshop (RAW).Google ScholarGoogle Scholar
  11. Free Software Foundation. GDB: The GNU Project Debugger. http://www.gnu.org/software/gdb/gdb.html.Google ScholarGoogle Scholar
  12. GateRocket, Inc. 2008. GateRocket product overview.Google ScholarGoogle Scholar
  13. IEEE. 2010. IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture. IEEE Std 1149.7-2009, c1--985.Google ScholarGoogle Scholar
  14. IETF. US Secure Hash Algorithm 1. (SHA1) RFC 3174. http://datatracker.ietf.org/doc/rfc3174.Google ScholarGoogle Scholar
  15. Iskander, Y., Patterson, C., and Craven, S. 2011. Improved abstractions and turnaround time for FPGA design validation and debug. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). 518--523. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Iskander, Y. S. 2012. Improved abstractions and turnaround time for FPGA design validation and debug. Ph.D. thesis, Virginia Polytechnic Institute and State University, Blacksburg, VA.Google ScholarGoogle Scholar
  17. Levi, D. and Guccione, S. A. 1998. BoardScope: A debug tool for reconfigurable systems. In Configurable Computing: Technology and Applications, Proceedings of SPIE, vol. 3526, J. Schewel Ed., SPIE, Bellingham, WA, 239--246.Google ScholarGoogle Scholar
  18. Ludwin, A., Betz, V., and Padalia, K. 2008. High-quality, deterministic parallel placement for FPGAs on commodity hardware. In Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays (FPGA’08). ACM, New York, 14--23. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. MIPS Technologies, Inc. System Navigator EJTAG Probe plus iFlowtrace. http://www.mips.com/media/files/fsl/MIPS_System_Navigator_iFlowtrace_509.pdf.Google ScholarGoogle Scholar
  20. Nelson, B., Wirthlin, M., Hutchings, B., Athanas, P., and Bohner, S. 2008. Design Productivity for Configurable Computing. CSREA Press, 57--66.Google ScholarGoogle Scholar
  21. OpenCores.org. OpenCores. http://www.opencores.org.Google ScholarGoogle Scholar
  22. Oracle Corporation. OpenSPARC. http://www.opensparc.net.Google ScholarGoogle Scholar
  23. Patterson, C. and Guccione, S. 2001. JBits design abstractions. In Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’01). 251--252. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Price, D. 1995. Pentium FDIV flaw-lessons learned. IEEE Micro 15, 2, 86--88. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Raja Gopalan, S. 2010. Timing-aware automatic floorplanning of partially reconfigurable designs for accelerating FPGA productivity. M.S. thesis, Virginia Polytechnic Institute and State University, Blacksburg, VA.Google ScholarGoogle Scholar
  26. Sandbyte Technologies. FPGAXpose data sheet. http://www.sandbyte.com/FPGAXposeDataSheet.pdf.Google ScholarGoogle Scholar
  27. Sarkar, S., Dabral, S., Tiwari, P. K., and Mitra, R. S. 2009. Lessons and experiences with high-level synthesis. IEEE Design Test Computers 26, 4, 34--45. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Schalick, C. 2009. Debugging FPGA designs may be harder than you expect. EDN 54, 21, 23.Google ScholarGoogle Scholar
  29. Stinson, D. R. 2006. Cryptography Theory and Practice 3rd Ed. Chapman & Hall/CRC.Google ScholarGoogle Scholar
  30. Subbarayan, G. 2010. Automatic instantiation and timing-aware placement of bus macros for partially reconfigurable FPGA designs. M.S. thesis, Virginia Polytechnic Institute and State University, Blacksburg, VA.Google ScholarGoogle Scholar
  31. Synopsys, Inc. Fast, efficient RTL debug for programmable logic designs. http://www.synopsis.com/cgi-bid/sid/pdfdla/pdfr1.cgi?file=fe_rtl_debug_wp.pdf.Google ScholarGoogle Scholar
  32. Wirthlin, M., Nelson, B., Hutchings, B., Athanas, P., and Bohner, S. 2008. A research agenda for improving configurable computing design productivity. Tech. rep., NSF Center for High-Performance Reconfigurable Computing (CHREC), Salt Lake City, UT.Google ScholarGoogle Scholar
  33. Xilinx, Inc. a. DS449: LogiCORE IP fast simplex link (FSL) V20 Bus. http://www.xilinx.com/support/documentation/ip_documentation/fsl_v20.pdf.Google ScholarGoogle Scholar
  34. Xilinx, Inc. b. MicroBlaze Processor Reference Guide. http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/mb_ref_guide.pdf.Google ScholarGoogle Scholar
  35. Xilinx, Inc. c. UG190: Virtex-5 FPGA User Guide. http://www.xilinx.com/support/documentation/user_guides/ug190.pdf.Google ScholarGoogle Scholar
  36. Xilinx, Inc. d. UG628: Command Line Tools User Guide. http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/devref.pdf.Google ScholarGoogle Scholar
  37. Xilinx, Inc. e. Xilinx ChipScope Pro. http://www.xilinx.com/tools/cspro.htm.Google ScholarGoogle Scholar
  38. Xilinx, Inc. 2008. Development System Reference Guide v10.1 Ed. Xilinx, Inc.Google ScholarGoogle Scholar

Index Terms

  1. High-Level Abstractions and Modular Debugging for FPGA Design Validation

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in

    Full Access

    • Published in

      cover image ACM Transactions on Reconfigurable Technology and Systems
      ACM Transactions on Reconfigurable Technology and Systems  Volume 7, Issue 1
      February 2014
      117 pages
      ISSN:1936-7406
      EISSN:1936-7414
      DOI:10.1145/2589584
      • Editor:
      • Steve Wilton
      Issue’s Table of Contents

      Copyright © 2014 ACM

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 1 February 2014
      • Accepted: 1 November 2013
      • Revised: 1 August 2013
      • Received: 1 March 2013
      Published in trets Volume 7, Issue 1

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • research-article
      • Research
      • Refereed

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader
    About Cookies On This Site

    We use cookies to ensure that we give you the best experience on our website.

    Learn more

    Got it!