Abstract
Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide visibility and control of the different stages of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not allow the design to be run at full speed. Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. The developed approach provides two means of directly validating synthesized hardware designs. The first allows the original high-level model written in C or C++ to be directly coupled to the synthesized hardware, abstracting away the traditional gate-level view of designs. A high-level programmatic interface allows the synthesized design to be validated directly by the software reference model. The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger. This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a running design on an FPGA.
- Altera Corporation. a. Design debugging using the SignalTap II embedded logic analyzer. http://www.altera.com/literature/hb/qts/qts_qii53009.pdf.Google Scholar
- Altera Corporation. b. Quartus II incremental compilation for hierarchical and team-based design. http://www.altera.com/literature/hb/qts/qts_qii51015.pdf.Google Scholar
- ARM Ltd. ARM information center. http://infocenter.arm.com/.Google Scholar
- Chandrasekharan, A. 2010. Accelerating incremental floorplanning of partially reconfigurable designs to improve FPGA productivity. M.S. thesis, Virginia Polytechnic Institute and State University, Blacksburg, VA.Google Scholar
- Chandrasekharan, A., Rajagopalan, S., Subbarayan, G., Frangieh, T., Iskander, Y., Craven, S., and Patterson, C. 2010. Accelerating FPGA development through the automatic parallel application of standard implementation tools. In Proceedings of the International Conference on Field-Programmable Technology (FPT). 53--60.Google Scholar
- Colwell, R. P. 2006. The Pentium Chronicles: The People, Passion, and Politics behind Intel’s Landmark Chips. John Wiley & Sons, Inc., New York. Google Scholar
Digital Library
- Craven, S. D. 2008. Structured approach to dynamic computing application development. Ph.D. thesis, Virginia Polytechnic Institute and State University, Blacksburg, VA.Google Scholar
- de Dinechin, F. and Pasca, B. FloPoCo. http://flopoco.gforge.inria.fr/.Google Scholar
- EE Times. 2011. FPGA tool vendor GateRocket folds. EE Times. http://www.eetimes.com/electronics-news/4218492/FPGA-tool-vendor-GateRocker-folds.Google Scholar
- Frangieh, T., Chandrasekharan, A., Rajagopalan, S., Iskander, Y., Craven, S., and Patterson, C. 2010. PATIS: Using partial configuration to improve static FPGA design productivity. In Proceedings of the 17th Reconfigurable Architectures Workshop (RAW).Google Scholar
- Free Software Foundation. GDB: The GNU Project Debugger. http://www.gnu.org/software/gdb/gdb.html.Google Scholar
- GateRocket, Inc. 2008. GateRocket product overview.Google Scholar
- IEEE. 2010. IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture. IEEE Std 1149.7-2009, c1--985.Google Scholar
- IETF. US Secure Hash Algorithm 1. (SHA1) RFC 3174. http://datatracker.ietf.org/doc/rfc3174.Google Scholar
- Iskander, Y., Patterson, C., and Craven, S. 2011. Improved abstractions and turnaround time for FPGA design validation and debug. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). 518--523. Google Scholar
Digital Library
- Iskander, Y. S. 2012. Improved abstractions and turnaround time for FPGA design validation and debug. Ph.D. thesis, Virginia Polytechnic Institute and State University, Blacksburg, VA.Google Scholar
- Levi, D. and Guccione, S. A. 1998. BoardScope: A debug tool for reconfigurable systems. In Configurable Computing: Technology and Applications, Proceedings of SPIE, vol. 3526, J. Schewel Ed., SPIE, Bellingham, WA, 239--246.Google Scholar
- Ludwin, A., Betz, V., and Padalia, K. 2008. High-quality, deterministic parallel placement for FPGAs on commodity hardware. In Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays (FPGA’08). ACM, New York, 14--23. Google Scholar
Digital Library
- MIPS Technologies, Inc. System Navigator EJTAG Probe plus iFlowtrace. http://www.mips.com/media/files/fsl/MIPS_System_Navigator_iFlowtrace_509.pdf.Google Scholar
- Nelson, B., Wirthlin, M., Hutchings, B., Athanas, P., and Bohner, S. 2008. Design Productivity for Configurable Computing. CSREA Press, 57--66.Google Scholar
- OpenCores.org. OpenCores. http://www.opencores.org.Google Scholar
- Oracle Corporation. OpenSPARC. http://www.opensparc.net.Google Scholar
- Patterson, C. and Guccione, S. 2001. JBits design abstractions. In Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’01). 251--252. Google Scholar
Digital Library
- Price, D. 1995. Pentium FDIV flaw-lessons learned. IEEE Micro 15, 2, 86--88. Google Scholar
Digital Library
- Raja Gopalan, S. 2010. Timing-aware automatic floorplanning of partially reconfigurable designs for accelerating FPGA productivity. M.S. thesis, Virginia Polytechnic Institute and State University, Blacksburg, VA.Google Scholar
- Sandbyte Technologies. FPGAXpose data sheet. http://www.sandbyte.com/FPGAXposeDataSheet.pdf.Google Scholar
- Sarkar, S., Dabral, S., Tiwari, P. K., and Mitra, R. S. 2009. Lessons and experiences with high-level synthesis. IEEE Design Test Computers 26, 4, 34--45. Google Scholar
Digital Library
- Schalick, C. 2009. Debugging FPGA designs may be harder than you expect. EDN 54, 21, 23.Google Scholar
- Stinson, D. R. 2006. Cryptography Theory and Practice 3rd Ed. Chapman & Hall/CRC.Google Scholar
- Subbarayan, G. 2010. Automatic instantiation and timing-aware placement of bus macros for partially reconfigurable FPGA designs. M.S. thesis, Virginia Polytechnic Institute and State University, Blacksburg, VA.Google Scholar
- Synopsys, Inc. Fast, efficient RTL debug for programmable logic designs. http://www.synopsis.com/cgi-bid/sid/pdfdla/pdfr1.cgi?file=fe_rtl_debug_wp.pdf.Google Scholar
- Wirthlin, M., Nelson, B., Hutchings, B., Athanas, P., and Bohner, S. 2008. A research agenda for improving configurable computing design productivity. Tech. rep., NSF Center for High-Performance Reconfigurable Computing (CHREC), Salt Lake City, UT.Google Scholar
- Xilinx, Inc. a. DS449: LogiCORE IP fast simplex link (FSL) V20 Bus. http://www.xilinx.com/support/documentation/ip_documentation/fsl_v20.pdf.Google Scholar
- Xilinx, Inc. b. MicroBlaze Processor Reference Guide. http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/mb_ref_guide.pdf.Google Scholar
- Xilinx, Inc. c. UG190: Virtex-5 FPGA User Guide. http://www.xilinx.com/support/documentation/user_guides/ug190.pdf.Google Scholar
- Xilinx, Inc. d. UG628: Command Line Tools User Guide. http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/devref.pdf.Google Scholar
- Xilinx, Inc. e. Xilinx ChipScope Pro. http://www.xilinx.com/tools/cspro.htm.Google Scholar
- Xilinx, Inc. 2008. Development System Reference Guide v10.1 Ed. Xilinx, Inc.Google Scholar
Index Terms
High-Level Abstractions and Modular Debugging for FPGA Design Validation
Recommendations
Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug
FPL '11: Proceedings of the 2011 21st International Conference on Field Programmable Logic and ApplicationsRapidly increasing FPGA density and complexity has heightened the need for higher levels of abstraction in validation and more rapid, focused approaches for design inspection. We present two methods of validating and debugging active, implemented FPGA ...
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems
The growth of the Reconfigurable Computing (RC) systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Low-level design tools are increasingly required for RC bitstream debugging and IP ...






Comments