Abstract
With the advent of multicore architectures, worst-case execution time (WCET) analysis has become an increasingly difficult problem. In this article, we propose a unified WCET analysis framework for multicore processors featuring both shared cache and shared bus. Compared to other previous works, our work differs by modeling the interaction of shared cache and shared bus with other basic microarchitectural components (e.g., pipeline and branch predictor). In addition, our framework does not assume a timing anomaly free multicore architecture for computing the WCET. A detailed experiment methodology suggests that we can obtain reasonably tight WCET estimates in a wide range of benchmark programs.
- T. Austin, E. Larson, and D. Ernst. 2002. SimpleScalar: An infrastructure for computer system modeling. Computer 35, 2 (2002). Google Scholar
Digital Library
- G. Balakrishnan and T. W. Reps. 2004. Analyzing memory accesses in x86 executables. In Compiler Construction (CC). Lecture Notes in Computer Science, vol. 2985, Springer, pp. 5--23.Google Scholar
Cross Ref
- C. Berg. 2006. PLRU cache domino effects. In Proceedings of the International Workshop on Worst-Case Execution Time (WCET) Analysis.Google Scholar
- S. Chattopadhyay, L. K. Chong, A. Roychoudhury, T. Kelter, P. Marwedel, and H. Falk. 2011. Chronos for multi-cores: A WCET analysis tool for multi-cores. http://www.comp.nus.edu.sg/∼rpembed/chronos/publication/chronos-multi-core.pdf.Google Scholar
- S. Chattopadhyay and A. Roychoudhury. 2009. Unified cache modeling for WCET analysis and layout optimizations. In Proceedings of the IEEE Real-Time Systems Symposium. Google Scholar
Digital Library
- S. Chattopadhyay and A. Roychoudhury. 2011. Scalable and precise refinement of cache timing analysis via model checking. In Proceedings of the IEEE Real-Time Systems Symposium. Google Scholar
Digital Library
- S. Chattopadhyay, A. Roychoudhury, and T. Mitra. 2010. Modeling shared cache and bus in multi core platforms for timing analysis. In Proceedings of the International Workshop on Software & Compilers for Embedded Systems. Google Scholar
Digital Library
- K. Goossens and A. Hansson. 2010. The aethereal network on chip after ten years: Goals, evolution, lessons, and future. In Proceedings of the 47th Design Automation Conference. Google Scholar
Digital Library
- D. Grund and J. Reineke. 2009. Abstract interpretation of FIFO replacement. In Proceedings of the Static Analysis Symposium. Google Scholar
Digital Library
- D. Grund and J. Reineke. 2010a. Precise and efficient FIFO-replacement analysis based on static phase detection. In Proceedings of the Euromicro Conference on Real-Time Systems. Google Scholar
Digital Library
- D. Grund and J. Reineke. 2010b. Toward precise PLRU cache analysis. In Proceedings of the International Workshop on Worst-Case Execution Time (WCET) Analysis.Google Scholar
- D. Grund, J. Reineke, and G. Gebhard. 2011. Branch target buffers: WCET analysis framework and timing predictability. J. Syst. Archit. Embed. Syst. Des. 57, 6. Google Scholar
Digital Library
- J. Gustafsson, A. Betts, A. Ermedahl, and B. Lisper. 2010. The Mälardalen WCET benchmarks -- Past, present and future. In Proceedings of the International Workshop on Worst-Case Execution Time (WCET) Analysis. http://www.mrtc.mdh.se/projects/wcet/benchmarks.html.Google Scholar
- D. Hardy, T. Piquet, and I. Puaut. 2009. Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches. In Proceedings of the IEEE Real-Time Systems Symposium. Google Scholar
Digital Library
- D. Hardy and I. Puaut. 2011. WCET analysis of instruction cache hierarchies. J. Syst. Archit. Embed. Syst. Des. 57, 7. Google Scholar
Digital Library
- B. K. Huynh, L. Ju, and A. Roychoudhury. 2011. Scope-aware data cache analysis for WCET estimation. In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium. Google Scholar
Digital Library
- T. Kelter, H. Falk, P. Marwedel, S. Chattopadhyay, and A. Roychoudhury. 2011. Bus aware multicore WCET analysis through TDMA offset bounds. In Proceedings of the Euromicro Conference on Real-Time Systems. Google Scholar
Digital Library
- X. Li, Y. Liang, T. Mitra, and A. Roychoudhury. 2007. Chronos: A timing analyzer for embedded software. Sci. Comput. Prog. http://www.comp.nus.edu.sg/∼rpembed/chronos. Google Scholar
Digital Library
- X. Li, T. Mitra, and A. Roychoudhury. 2005. Modeling control speculation for timing analysis. Real-Time Syst. 29, 1. Google Scholar
Digital Library
- X. Li, A. Roychoudhury, and T. Mitra. 2006. Modeling out-of-order processors for WCET analysis. Real-Time Syst. 34, 3. Google Scholar
Digital Library
- Y. Li, V. Suhendra, Y. Liang, T. Mitra, and A. Roychoudhury. 2009. Timing analysis of concurrent programs running on shared cache multi-cores. In Proceedings of the IEEE Real-Time Systems Symposium. Google Scholar
Digital Library
- Y-T. S. Li, S. Malik, and A. Wolfe. 1999. Performance estimation of embedded software with instruction cache modeling. ACM Trans. Des. Autom. Electron. Syst. 4, 3. Google Scholar
Digital Library
- T. Lundqvist and P. Stenström. 1999. Timing anomalies in dynamically scheduled microprocessors. In Proceedings of the IEEE Real-Time Systems Symposium. Google Scholar
Digital Library
- M. Lv, G. Nan, W. Yi, and G. Yu. 2010. Combining abstract interpretation with model checking for timing analysis of multicore software. In Proceedings of the IEEE Real-Time Systems Symposium. Google Scholar
Digital Library
- C. Maiza and C. Rochange. 2011. A framework for the timing analysis of dynamic branch predictors. In Proceedings of the 19th International Conference on Real-Time and Network Systems (RTNS 2011). 65--74.Google Scholar
- M. Paolieri, E. Quiñones, F. J. Cazorla, G. Bernat, and M. Valero. 2009. Hardware support for WCET analysis of hard real-time multicore systems. In Proceedings of the International Symposium on Computer Architecture. Google Scholar
Digital Library
- R. Pellizzoni, E. Betti, S. Bak, G. Yao, J. Criswell, M. Caccamo, and R. Kegley. 2011. A predictable execution model for COTS-based embedded systems. In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium. Google Scholar
Digital Library
- J. Reineke, D. Grund, C. Berg, and R. Wilhelm. 2007. Timing predictability of cache replacement policies. Real-Time Syst. 37, 2. Google Scholar
Digital Library
- C. Rochange and P. Sainrat. 2009. A context-parameterized model for static analysis of execution times. In Transactions of High-Performance Embedded Architectures and Compilers II (T. HiPEAC 2). Lecture Notes in Computer Science, vol. 5470, Springer, 222--241. Google Scholar
Digital Library
- J. Rosen, A. Andrei, P. Eles, and Z. Peng. 2007. Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip. In Proceedings of the IEEE Real-Time Systems Symposium. Google Scholar
Digital Library
- R. Sen and Y. N. Srikant. 2007. WCET estimation for executables in the presence of data caches. In Proceedings of the 7th ACM and IEEE International Conference on Embedded Software (EMSOFT'07). ACM, New York, 203--212. Google Scholar
Digital Library
- H. Theiling, C. Ferdinand, and R. Wilhelm. 2000. Fast and precise WCET prediction by separated cache and path analyses. Real-Time Syst. 18, 2/3. Google Scholar
Digital Library
- R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand. 2009. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. IEEE Trans. CAD of Integ. Circ. Syst. 28, 7. Google Scholar
Digital Library
- J. Yan and W. Zhang. 2008. WCET Analysis for multi-core processors with shared L2 instruction caches. In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium. Google Scholar
Digital Library
- M. M. Zahran, K. Albayraktaroglu, and M. Franklin. 2007. Non-inclusion property in multi-level caches revisited. Int. J. Comput. Appl. 14, 2.Google Scholar
Index Terms
A Unified WCET analysis framework for multicore platforms
Recommendations
Hardware support for WCET analysis of hard real-time multicore systems
The increasing demand for new functionalities in current and future hard real-time embedded systems like automotive, avionics and space industries is driving an increase in the performance required in embedded processors. Multicore processors represent ...
A Unified WCET Analysis Framework for Multi-core Platforms
RTAS '12: Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications SymposiumWith the advent of multi-core architectures, worst case execution time (WCET) analysis has become an increasingly difficult problem. In this paper, we propose a unified WCET analysis framework for multi-core processors featuring both shared cache and ...
Hardware support for WCET analysis of hard real-time multicore systems
ISCA '09: Proceedings of the 36th annual international symposium on Computer architectureThe increasing demand for new functionalities in current and future hard real-time embedded systems like automotive, avionics and space industries is driving an increase in the performance required in embedded processors. Multicore processors represent ...






Comments