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Design Tools for Implementing Self-Aware and Fault-Tolerant Systems on FPGAs

Published:04 July 2014Publication History
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Abstract

To fully exploit the capabilities of runtime reconfigurable FPGAs in self-aware systems, design tools are required that exceed the capabilities of present vendor design tools. Such tools must allow the implementation of scalable reconfigurable systems with various different partial modules that might be loaded to different positions of the device at runtime. This comprises several complex tasks, including floorplanning, communication architecture synthesis, physical constraints generation, physical implementation, and timing verification all the way down to the final bitstream generation. In this article, we present how our GoAhead framework helps in implementing self-aware systems on FPGAs with a minimum of user interaction.

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    • Published in

      cover image ACM Transactions on Reconfigurable Technology and Systems
      ACM Transactions on Reconfigurable Technology and Systems  Volume 7, Issue 2
      June 2014
      199 pages
      ISSN:1936-7406
      EISSN:1936-7414
      DOI:10.1145/2638850
      Issue’s Table of Contents

      Copyright © 2014 ACM

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 4 July 2014
      • Accepted: 1 March 2014
      • Revised: 1 June 2013
      • Received: 1 January 2013
      Published in trets Volume 7, Issue 2

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