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Imprecise Datapath Design: An Overclocking Approach

Published:17 March 2015Publication History
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Abstract

In this article, we describe an alternative circuit design methodology when considering trade-offs between accuracy, performance, and silicon area. We compare two different approaches that could trade accuracy for performance. One is the traditional approach where the precision used in the datapath is limited to meet a target latency. The other is a proposed new approach which simply allows the datapath to operate without timing closure. We demonstrate analytically and experimentally that on average our approach obtains either smaller errors or equivalent faster operating frequencies in comparison to the traditional approach. This is because the worst case caused by timing violations only happens rarely, while precision loss results in errors to most data. We also show that for basic arithmetic operations such as addition, applying our approach to the simple building block of ripple carry adders can achieve better accuracy or performance than using faster adder designs to achieve similar latency.

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    • Published in

      cover image ACM Transactions on Reconfigurable Technology and Systems
      ACM Transactions on Reconfigurable Technology and Systems  Volume 8, Issue 2
      Special Section on FPL 2013
      April 2015
      129 pages
      ISSN:1936-7406
      EISSN:1936-7414
      DOI:10.1145/2746532
      • Editor:
      • Steve Wilton
      Issue’s Table of Contents

      Copyright © 2015 ACM

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 17 March 2015
      • Accepted: 1 April 2014
      • Revised: 1 February 2014
      • Received: 1 September 2013
      Published in trets Volume 8, Issue 2

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