Abstract
Field-programmable gate arrays (FPGAs) are increasingly susceptible to radiation-induced single event upsets (SEUs). These upsets are predominant in a space environment; however, with increasing use of static RAM (SRAM) in modern FPGAs, these SEUs are gaining prominence even in a terrestrial environment. SEUs can flip SRAM bits of FPGA, potentially altering the functionality of the implemented design. This has motivated FPGA designers to investigate techniques to protect the FPGA configuration bits against such inadvertent bit flips (soft error). Traditionally, triple modular redundancy (TMR) is used to protect the FPGA bit flips. Increasing design complexity and limited battery life motivate for alternative approaches for soft-error tolerance. In this article, we propose a technique to improve autonomous fault-masking capabilities of a design by maximizing the number of zeros or ones in lookup tables (LUTs). The technique analyzes critical configuration bits and utilizes spare resources (XOR gates and carry chains) of FPGAs to selectively manipulate the logic implemented in LUTs using two operations: LUT restructuring and LUT decomposition. We implemented the proposed approach for Xilinx Virtex-6 FPGAs and validated the same with a wide set of designs from the MCNC, IWLS 2005, and ITC99 benchmark suites. Results demonstrate that the proposed logic restructuring maximizes logic 0 (or 1) of LUTs by an average of 20%, achieving 80% fault masking with no area overhead. The fault rate of the entire design is reduced by 60% on average as compared to the existing techniques. Furthermore, the logic decomposition algorithm provides incremental fault-tolerance capabilities and achieves an additional 5% fault masking with an average 7% increase in slice usage.
The complete methodology is implemented into a tool for Xilinx FPGA and is made available online for the benefit of the research community. The algorithms are lightweight, and the whole design flow (including Xilinx Place and Route) was completed in 75 minutes for the largest benchmark in the set.
- C. Beckhoff, D. Koch, and J. Torresen. 2011. The Xilinx design language (XDL): Tutorial and use cases. In Proceedings of the International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC).Google Scholar
- J. Cong and K. Minkovich. 2010. LUT-based FPGA technology mapping for reliability. In Proceedings of the ACM Design Automation Conference (DAC). Google Scholar
Digital Library
- A. Das, S. Venkataraman, and A. Kumar. 2013. Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). 1--8. DOI:http://dx.doi.org/10.1109/FPL.2013.6645498Google Scholar
- Z. Feng, Y. Hu, L. He, and R. Majumdar. 2009. IPR: In-place reconfiguration for FPGA fault tolerance. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD). Google Scholar
Digital Library
- J. B. Ferron, L. Anghel, R. Leveugle, A. Bocquillon, F. Miller, and G. Mantelet. 2009. A methodology and tool for predictive analysis of configuration bit criticality in SRAM-based FPGAS: Experimental results. In Proceedings of the International Conference on Signals, Circuits, and Systems (SCS). 1--6. DOI:http://dx.doi.org/10.1109/ICSCS.2009.5412330Google Scholar
- K. Huang, Y. Hu, X. Li, G. Hua, H. Liu, and B. Liu. 2011. Exploiting free LUT entries to mitigate soft errors in SRAM-based FPGAs. In Proceedings of the IEEE Asian Test Symposium (ATS). Google Scholar
Digital Library
- F. L. Kastensmidt, L. Sterpone, L. Carro, and M. S. Reorda. 2005. On the optimal design of triple modular redundancy logic for SRAM-based FPGAs. In Proceedings of the IEEE Conference on Design, Automation, and Test in Europe (DATE). Google Scholar
Digital Library
- C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. Nelson, and B. Hutchings. 2011. RapidSmith: Do-it-yourself CAD tools for Xilinx FPGAs. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). Google Scholar
Digital Library
- J.-Y. Lee, Z. Feng, and L. He. 2010a. In-place decomposition for robustness in FPGA. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD). Google Scholar
Digital Library
- J.-Y. Lee, Y. Hu, R. Majumdar, L. He, and M. Li. 2010b. Fault-tolerant resynthesis with dual-output LUTs. In Proceedings of the IEEE Asia and South Pacific Design Automation Conference (ASP-DAC). Google Scholar
Digital Library
- F. Lima, L. Carro, and R. Reis. 2003. Designing fault tolerant systems into SRAM-based FPGAs. In Proceedings of the ACM Design Automation Conference (DAC). Google Scholar
Digital Library
- A. Mishchenko, B. Steinbach, and M. Perkowski. 2001. An algorithm for bi-decomposition of logic functions. In Proceedings of the ACM Design Automation Conference (DAC). Google Scholar
Digital Library
- A. Mishchenko, X. Wang, and T. Kam. 2003. A new-enhanced constructive decomposition and mapping algorithm. In Proceedings of the ACM Design Automation Conference (DAC). Google Scholar
Digital Library
- C. D. Patterson, P. Sundararajan, B. J. Blodget, and S. P. McMillan. 2008. Method and system for identifying essential configuration bits. U.S. Patent 7,406,673.Google Scholar
- J. Safaei and H. Beigy. 2007. Quine-McCluskey classification. In Proceedings of the IEEE/ACS International Conference on Computer Systems and Applications.Google Scholar
- T. Sasao and M. Matsuura. 2004. A method to decompose multiple-output logic functions. In Proceedings of the ACM Design Automation Conference (DAC). Google Scholar
Digital Library
- S. Srinivasan, A. Gayasen, N. Vijaykrishnan, M. Kandemir, Y. Xie, and M. J. Irwin. 2004. Improving soft-error tolerance of FPGA configuration bits. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD). Google Scholar
Digital Library
- Wiki. 2013. LUT-RD: LUT Restructuring and Decomposition. Available at http://wiki.nus.edu.sg/display/mpsoc/Documents and https://perf.wiki.kernel.org.Google Scholar
- D. Ziener, S. Assmus, and J. Teich. 2006. Identifying FPGA IP-cores based on lookup table content analysis. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). 1--6. DOI:http://dx.doi.org/10.1109/FPL.2006.311255Google Scholar
Index Terms
Autonomous Soft-Error Tolerance of FPGA Configuration Bits
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