skip to main content
research-article

Dynamic Energy, Performance, and Accuracy Optimization and Management Using Automatically Generated Constraints for Separable 2D FIR Filtering for Digital Video Processing

Published:29 December 2014Publication History
Skip Abstract Section

Abstract

There is strong interest in the development of dynamically reconfigurable systems that can meet real-time constraints on energy, performance, and accuracy. The generation of real-time constraints will significantly expand the applicability of dynamically reconfigurable systems to new domains, such as digital video processing.

We develop a dynamically reconfigurable 2D FIR filtering system that can meet real-time constraints in energy, performance, and accuracy (EPA). The real-time constraints are automatically generated based on user input, image types associated with video communications, and video content. We first generate a set of Pareto-optimal realizations, described by their EPA values and associated 2D FIR hardware description bitstreams. Dynamic management is then achieved by selecting Pareto-optimal realizations that meet the automatically generated time-varying EPA constraints.

We validate our approach using three different 2D Gaussian filters. Filter realizations are evaluated in terms of the required energy per frame, accuracy of the resulting image, and performance in frames per second. We demonstrate dynamic EPA management by applying a Difference of Gaussians (DOG) filter to standard video sequences. For video frame sizes that are equal to or larger than the VGA resolution, compared to a static implementation, our dynamic system provides significant reduction in the total energy consumption (>30%).

References

  1. Afandi Ahmad and Abbes Amira. 2009. Efficient reconfigurable architectures for 3D medical image compression. In Proceedings of International Conference on Field-Programmable Technology. 472--474.Google ScholarGoogle ScholarCross RefCross Ref
  2. M. S. Andrews. 1999. Architectures for generalized 2d FIR filtering using separable filter structures. In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP ‘99). 2215--2218. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Juergen Becker, Michael Huebner, and Michael Ullmann. 2003. Power estimation and power measurement of Xilinx Virtex FPGAs: Tradeoffs and limitations. In Proceedings of the 16th Symposium on Integrated Circuits and Systems Design. 283--288. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Sheetal U. Bhandari, Shaila Subbaraman, Shashank S. Pujari, and Rashmi Mahajan. 2009. Real time video processing on FPGA using on the fly partial reconfiguration. In Proceedings of the International Conference on Signal Processing Systems. 244--247. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Robin Bonamy, Daniel Chillet, Sébastien Bilavarn, and Olivier Sentieys. 2012. Power consumption model for partial and dynamic reconfiguration. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig’12). 1--8.Google ScholarGoogle ScholarCross RefCross Ref
  6. Kiran Bondalapati and Viktor K. Prasanna. 1999. Dynamic precision management for loop computations on reconfigurable architectures. In Proceedings of the 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. 249--258. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Sophie Bouchoux, El-Bay Bourennane, and Michael Paindavoine. 2004. Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA. In Proceedings of the International Conference on Image Processing. 2841--2844.Google ScholarGoogle Scholar
  8. Christos-S. Bouganis, Sung-Boem Park, George A. Constantinides, and Peter Y.K. Cheung. 2009. Synthesis and optimization of 2D filter designs for heterogeneous FPGAs. ACM Trans. Reconfig. Technol. Syst. 1, 4, Article 24 (Jan. 2009), 28 pages. DOI:http://dx.doi.org/10.1145/1462586.1462593 Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Alan Bovik (Ed.). 2009a. The Essential Guide to Image Processing (2nd ed.). Academic Press, Elsevier. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Alan Bovik (Ed.). 2009b. The Essential Guide to Video Processing (2nd ed.). Academic Press, Elsevier. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Wayne Burleson, Prashant Jain, and Subramanian Venkatraman. 2001. Dynamically parameterized architecture for power-aware video coding: Motion Estimation and DCT. In Proceedings of 2nd USF International Workshop on Digital and Computational Video. 8--12. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Roger Chamberlain, Eric Hemmeter, Robert Morley, and Jason White. 2003. Modeling the power consumption of audio signal processing computations using customized numerical representations. In Proceedings of the 36th Annual Simulation Symposium. 249--255. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. C. Claus, B. Zhang, W. Stechele, L. Braun, M. Hübner, and J. Becker. 2008. A multi-platform controller allowing for maximum dynamic partial reconfiguration throughput. In Proceedings of the International Conference on Field Programmable Logic and Applications. 535--538.Google ScholarGoogle Scholar
  14. Omkar Dandekar, William Plishker, Shuvra S. Bhattacharyya, and Raj Shekkar. 2008. Multiobjective optimization for reconfigurable implementation of medical image registration. Int. J. Reconfig. Comput. 2008, Article ID 738174, 17 pages.Google ScholarGoogle Scholar
  15. Mariano Fons, Francisco Fons, and Enrique Cantó. 2010. Fingerprint image processing acceleration through run-time reconfigurable hardware. IEEE Trans. Circuits Syst. II: Express Brief, 57, 12 (Dec. 2010), 991--995. DOI:http://dx.doi.org/10.1109/TCSII.2010.2087970 Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Hugo Hedberg, Petr Dokladal, and Viktor Öwall. 2009. Binary morphology with spatially variant structuring elements: Algorithm and architecture. IEEE Trans. Image Process. 18, 3 (March 2009), 562--572. DOI:http://dx.doi.org/10.1109/TIP.2008.2010108 Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. John C. Hoffman and M. Marios Pattichis. 2011. A high-speed dynamic partial reconfiguration controller using direct memory access through a multiport memory controller and overclocking with active feedback. Int. J. Reconfig. Comput. 2011, Article ID 439072, 10 pages.Google ScholarGoogle Scholar
  18. Sangjin Hong, Jinseok Lee, Akshay Athalye, Petar M. Djurić, and We-Duke Cho, W. 2007. Design methodology for domain specific parameterizable particle filter realizations. IEEE Trans. Circuits Syst. Part I: Regular Papers, 54, 9 (Sep. 2007), 1987--2000. DOI:http://dx.doi.org/10.1109/TCSI.2007.904690Google ScholarGoogle Scholar
  19. Yohei Hori, Akashi Satoh, Hirofumi Sakane, and Kenji Toda. 2008. Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems. In Proceedings of the International Conference on Field Programmable Logic and Applications. 23--28.Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Jian Huang and Jooheung Lee. 2009. A self-reconfigurable platform for scalable DCT computation using compressed partial bitstreams and BlockRAM prefetching. IEEE Trans. Circuits Syst. Video Technol. 19, 11 (Nov. 2009), 1623--1632. DOI:http://dx.doi.org/10.1109/TCSVT.2009.2031464 Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Takashi Komuro, Tomohira Tabata, and Masatoshi Ishikawa. 2010. A reconfigurable embedded system for 1000 f/s real-time vision. IEEE Trans. Circuits Syst. Video Technol. 20, 4 (April 2010), 496--504. DOI:http://dx.doi.org/10.1109/TCSVT.2009.2035832 Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Jahyun Koo, Alan C. Evans, and Warren J. Gross. 2009. 3-D brain MRI tissue classification on FPGAs. IEEE Trans. Image Process. 18, 12 (Dec. 2009), 2735--2746. DOI:http://dx.doi.org/10.1109/TIP.2009.2028926 Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Ming Liu, Wolfgang Kuehn, Zhonghai Lu, and Axel Jantsch. 2009. Run-time partial reconfiguration speed investigation and architectural design space exploration. In Proceedings of the International Conference on Field Programmable Logic and Applications. 498--502.Google ScholarGoogle ScholarCross RefCross Ref
  24. Yong Liu and Edmund M-K. Lai. 2004. Design and Implementation of an RNS-based 2-D DWT processor. IEEE Trans. Consum. Electron. 50, 1 (Feb. 2004), 376--385. DOI: http://dx.doi.org/10.1109/TCE.2004.1277887 Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Daniel Llamocca and Marios Pattichis. 2013. A dynamically reconfigurable pixel processor system based on power/energy-performance-accuracy optimization. IEEE Trans. Circuits Syst. Video Technol. 23, 3 (March 2013), 488--502. DOI: http://dx.doi.org/10.1109/TCSVT.2012.2210664 Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Daniel Llamocca, Marios Pattichis, and Alonzo Vera. 2010. Partial reconfigurable FIR filtering system using distributed arithmetic. Int. J. Reconfig. Comput. 2010, Article ID 357978, 14 pages. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. Daniel Llamocca and Marios Pattichis. 2010. Real-time dynamically reconfigurable 2-D filterbanks. In Proceedings of 2010 IEEE Southwest Symposium on Image Analysis & Interpretation. 181--184.Google ScholarGoogle ScholarCross RefCross Ref
  28. Daniel Llamocca, Cesar Carranza, and Marios Pattichis. 2011. Separable FIR filtering in FPGA and GPU implementations: Energy, performance, and accuracy considerations. In Proceedings of the International Conference on Field Programmable Logic and Applications. 363--368. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Daniel Llamocca, Cesar Carranza, and Marios Pattichis. 2012. Dynamic multiobjective optimization management of the energy-performance-accuracy space for separable 2-D complex filters. In Proceedings of the International Conference on Field Programmable Logic and Applications, 579--582.Google ScholarGoogle ScholarCross RefCross Ref
  30. David G. Lowe. 1999. Object recognition from local scale-invariant features. In Proceedings of the 7th IEEE International Conference on Computer Vision. 1150--1157. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. David G. Lowe. 2004. Distinctive image features from scale-invariant keypoints. Int. J. Comput. Vision 60, 2 (Nov. 2004), 91--110. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. Hong S. Neoh and Asher Hazanchuk. 2004. Adaptive edge detection for real-time video processing using FPGAs. In Proceeding of the GSPx2004 Conference.Google ScholarGoogle Scholar
  33. Duy Nguyen, David Halupka, Parham Aarabi, and Ali Sheikholeslami. 2006. Real-time face detection and lip feature extraction using field programmable gate arrays. IEEE Trans. Syst. Man Cybern. 36, 4 (Aug. 2006), 902--912. DOI:http://dx.doi.org/10.1109/TSMCB.2005.862728 Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. Juanjo Noguera and Irwin O. Kennedy. 2007. Power reduction in network equipment through adaptive partial reconfiguration. In Proceedings of the International Conference on Field Programmable Logic and Applications. 240--245.Google ScholarGoogle Scholar
  35. Erdal Oruklu and Jafar Saniie. 2009. Dynamically reconfigurable architecture design for ultrasonic imaging. IEEE Trans. Instrum. Meas. 58, 8 (Aug. 2009), 2856--2866. DOI: http://dx.doi.org/10.1109/TIM.2009.2016370Google ScholarGoogle ScholarCross RefCross Ref
  36. Tamás Raikovich and Béla Fehér. 2010. Application of partial reconfiguration of FPGAs in image processing. In Proceedings of 2010 Conference on Ph.D. Research in Microelectronics and Electronics. 1--4.Google ScholarGoogle Scholar
  37. Javier Resano, Daniel Mozos, Diederik Verkest, Serge Vernalde, and Francky Catthoor. 2003. Runtime minimization of reconfiguration overhead in dynamically reconfigurable systems. In Proceedings of the International Conference on Field Programmable Logic and Applications, 585--594.Google ScholarGoogle ScholarCross RefCross Ref
  38. Arvind Sudarsanam, Robert Barnes, Jeff Carver, Ramachandra Kallam, and Aravind Dasu. 2010. Dynamically reconfigurable systolic array accelerators: A case study with extended Kalman filter and discrete wavelet transform algorithms. IET Comput. Digit. Tech. 4, 2 (March 2010), 126--142. DOI:http://dx.doi.org/10.1049/iet-cdt.2008.0139Google ScholarGoogle ScholarCross RefCross Ref
  39. Robert Turney. 2007. Two-Dimensional Linear Filtering (XAPP933). v1.1 ed., Xilinx Inc., San Jose, CA.Google ScholarGoogle Scholar
  40. Alonzo Vera, Marios Pattichis, and James Lyke. 2011. A dynamic dual fixed-point arithmetic architecture for FPGAs. Int. J. Reconfig. Comput., 2011, Article ID 518602, 19 pages.Google ScholarGoogle ScholarCross RefCross Ref
  41. Xilinx. 2010a. Partial Reconfiguration User Guide for ISE 12.3 (UG702). v12.3 ed., Xilinx Inc., San Jose, CA.Google ScholarGoogle Scholar
  42. Xilinx. 2010b. Virtex-6 Family Overview (DS150). v2.2 ed., Xilinx Inc., San Jose, CA.Google ScholarGoogle Scholar
  43. Xilinx 2011. Power Methodology Guide (UG786). v13.1 ed., Xilinx Inc., San Jose, CA.Google ScholarGoogle Scholar
  44. Huaqiu Yang, Fanjiong Zhang, JinMei Lai, and Yan Wang. 2010. Image filtering using partially and dynamically reconfiguration. In Proceedings of the International Conference on Solid-State and Integrated Circuit Technology. 2067--2073.Google ScholarGoogle ScholarCross RefCross Ref

Index Terms

  1. Dynamic Energy, Performance, and Accuracy Optimization and Management Using Automatically Generated Constraints for Separable 2D FIR Filtering for Digital Video Processing

          Recommendations

          Comments

          Login options

          Check if you have access through your login credentials or your institution to get full access on this article.

          Sign in

          Full Access

          • Published in

            cover image ACM Transactions on Reconfigurable Technology and Systems
            ACM Transactions on Reconfigurable Technology and Systems  Volume 7, Issue 4
            January 2015
            213 pages
            ISSN:1936-7406
            EISSN:1936-7414
            DOI:10.1145/2699137
            • Editor:
            • Steve Wilton
            Issue’s Table of Contents

            Copyright © 2014 ACM

            Publisher

            Association for Computing Machinery

            New York, NY, United States

            Publication History

            • Published: 29 December 2014
            • Accepted: 1 April 2014
            • Revised: 1 June 2013
            • Received: 1 July 2012
            Published in trets Volume 7, Issue 4

            Permissions

            Request permissions about this article.

            Request Permissions

            Check for updates

            Qualifiers

            • research-article
            • Research
            • Refereed

          PDF Format

          View or Download as a PDF file.

          PDF

          eReader

          View online with eReader.

          eReader
          About Cookies On This Site

          We use cookies to ensure that we give you the best experience on our website.

          Learn more

          Got it!