skip to main content
research-article

Composing Multi-Ported Memories on FPGAs

Published:03 September 2014Publication History
Skip Abstract Section

Abstract

Multi-ported memories are challenging to implement on FPGAs since the block RAMs included in the fabric typically have only two ports. Hence we must construct memories requiring more than two ports, either out of logic elements or by combining multiple block RAMs. We present a thorough exploration and evaluation of the design space of FPGA-based soft multi-ported memories for conventional solutions, and also for the recently proposed Live Value Table (LVT) [LaForest and Steffan 2010] and XOR [LaForest et al. 2012] approaches to unidirectional port memories, reporting results for both Altera and Xilinx FPGAs. Additionally, we thoroughly evaluate and compare with a recent LVT-based approach to bidirectional port memories [Choi et al. 2012].

References

  1. Altera. 2003. Mercury programmable logic device family data sheet. http://www.altera.com/ds/archives/dsmercury.pdf.Google ScholarGoogle Scholar
  2. Altera. 2011. Nios II processor reference handbook. http://www.altera.com/literature/hb/nios2/n2cpu_nii5v1.pdf.Google ScholarGoogle Scholar
  3. Altera. 2012. DC and switching characteristics for stratix iv devices. http://www.altera.com/literature/hb/stratix-iv/stx4siv54001.pdf.Google ScholarGoogle Scholar
  4. Fakhar Anjam, Muhammad Nadeem, and Stephan Wong. 2010a. A VLIW softcore processor with dynamically adjustable issue-slots. In Proceedings of the International Conference on Field-Programmable Technology (FPT'10). 393--398.Google ScholarGoogle ScholarCross RefCross Ref
  5. Fakhar Anjam, Stephan Wong, and Faisal F. Nadeem. 2010b. A multiported register file with register renaming for configurable softcore VLIW processors. In Proceedings of the International Conference on Field-Programmable Technology (FPT'10). 403--408.Google ScholarGoogle Scholar
  6. Roberto Carli. 2008. Flexible mips soft processor architecture. http://hdl.handle.net/1721.1/41874.Google ScholarGoogle Scholar
  7. Jongsok Choi, Kevin Nam, Andrew Canis, Jason Anderson, Stephan Brown, and Tomasz Czajkowski. 2012. Impact of cache architecture on speed and area of FPGA-based processor/parallel-accelerator systems. In Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM'12). 17--24. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Blair Fort, Davor Capalija, Zvonko G. Vranesic, and Stephan D. Brown. 2006. A multithreaded soft processor for SOPC area reduction. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06). 131--142. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Mitchell Hayenga and Mikko Lipasti. 2011. The NOX router. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'11). 36--46. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, and John Foster. 2005. An FPGA-based VLIW processor with custom hardware execution. In Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA'05). 107--117. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Sachin Katti, Hariharan Rahul, Wenjun Hu, Dina Katabi, Muriel Medard, and Jon Crowcroft. 2006. XORs in the air: Practical wireless network coding. In Proceedings of the Conference on Applications, Technologies, Architectures, and Protocols for Computer Communications (SIGCOMM'06). 243--254. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Charles Eric Laforest, Ming Gang Liu, Emma Rapati, and J. Gregory Steffan. 2012. Multi-ported memories for FPGAs via XOR. In Proceedings of the 20th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'12). 209--218. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Charles Eric Laforest and J. Gregory Steffan. 2010. Efficient multi-ported memories for FPGAs. In Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'10). 41--50. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Naraig Manjikian. 2003. Design issues for prototype implementation of a pipelined superscalar processor in programmable logic. In Proceedings of the IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM'03). 155--158.Google ScholarGoogle ScholarCross RefCross Ref
  15. Roger Moussali, Nabil Ghanem, and Mazen A. R. Saghir. 2007. Supporting multithreading in configurable soft processor cores. In Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'07). 155--159. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Vignyan Reddy Kothinti Naresh, David J. Palframan, and Mikko H. Lipasti. 2011. CRAM: Coded registers for amplified multiporting. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'11). 196--205. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. David A. Patterson, Garth Gibson, and Randy H. Katz. 1988. A case for redundant arrays of inexpensive disks (raid). In Proceedings of the ACM SIGMOD International Conference on Management of Data (SIGMOD'88). 109--116. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. James R. Phillips. 2012. Py2eq curve-fitting library. http://code.google.com/p/pyeq2/.Google ScholarGoogle Scholar
  19. Mazen Saghir and Rawan Naous. 2007. A configurable multi-ported register file architecture for soft processor cores. In Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC'07). Springer, 14--25. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Mazen A. R. Saghir, Mohamad El-Majzoub, and Patrick Akl. 2006. Datapath and ISA customization for soft vliw processors. In Proceedings of the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig'06). 1--10.Google ScholarGoogle ScholarCross RefCross Ref
  21. Henry Wong, Vaughn Betz, and Jonathan Rose. 2011. Comparing FPGA vs. custom CMOS and the impact on processor microarchitecture. In Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'11). 5--14. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Xilinx. 2012. Virtex-6 FPGA data sheet: DC and switching characteristics. http://www.xilinx.com/support/documentation/data sheets/ds152.pdf.Google ScholarGoogle Scholar
  23. Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose. 2006. Application-specific customization of soft processor microarchitecture. In Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays (FPGA'06). 201--210. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Composing Multi-Ported Memories on FPGAs

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in

    Full Access

    • Published in

      cover image ACM Transactions on Reconfigurable Technology and Systems
      ACM Transactions on Reconfigurable Technology and Systems  Volume 7, Issue 3
      Special Issue on 11th International Conference on Field-Programmable Technology (FPT'12) and Special Issue on the 7th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC'12)
      August 2014
      199 pages
      ISSN:1936-7406
      EISSN:1936-7414
      DOI:10.1145/2664590
      Issue’s Table of Contents

      Copyright © 2014 ACM

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 3 September 2014
      • Accepted: 1 February 2014
      • Revised: 1 December 2013
      • Received: 1 August 2013
      Published in trets Volume 7, Issue 3

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • research-article
      • Research
      • Refereed

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader
    About Cookies On This Site

    We use cookies to ensure that we give you the best experience on our website.

    Learn more

    Got it!