Abstract
Placement is though as the most time-consuming processes in physical implementation flows for reconfigurable architectures, while it highly affects the quality of derived application implementation, as it has impact on the maximum operating frequency. Throughout this article, we propose a novel placer, based on genetic algorithm, targeting to FPGAs. Rather than relevant approaches, which are executed sequentially, the new placer exhibits inherent parallelism, which can benefit from multicore processors. Experimental results prove the effectiveness of this solution, as it achieves average reduction of execution runtime and application’s delay by 67× and 16%, respectively.
- Cristinel Ababei. 2009. Speeding up FPGA placement via partitioning and multithreading. Int. J. Reconfig. Comp. Google Scholar
Digital Library
- Gene M. Amdahl. 1967. Validity of the single processor approach to achieving large scale computing capabilities. In Proceedings of the AFIPS Spring Joint Computing Conference, Vol. 30. 483--485. Google Scholar
Digital Library
- Vaughn Betz and Jonathan Rose. 1997. VPR: A new packing, placement and routing tool for FPGA research. In FPL. Lecture Notes in Computer Science. Springer, 213--222. Google Scholar
Digital Library
- Vaughn Betz, Jonathan Rose, and Alexander Marquardt (Eds.). 1999. Architecture and CAD for Deep-Submicron FPGAs. Springer, New York, NY. Google Scholar
Digital Library
- Andrea Casotto, Fabio Romeo, and Alberto L. Sangiovanni-Vincentelli. 1987. A parallel simulated annealing algorithm for the placement of macro-cells. IEEE Trans. CAD Integr. Circuits Syst. 6, 5, 838--847. Google Scholar
Digital Library
- Alexander Choong, Rami Beidas, and Jianwen Zhu. 2010. Parallelizing simulated annealing-based placement using GPGPU. In FPL. IEEE, 31--34. Google Scholar
Digital Library
- Paul Darwen and Xin Yao. 1995. A dilemma for fitness sharing with a scaling function. In Proc. of the 1995 IEEE Int’l Conf. on Evolutionary Computation (ICEC’95). IEEE Press, 166--171.Google Scholar
Cross Ref
- D. Diamantopoulos, K. Siozios, S. Xydis, and D. Soudris. 2013. A framework for supporting parallel application placement onto reconfigurable platforms. In Proceedings of the PARMA Workshop, HiPEAC Conference, Berlin, Germany.Google Scholar
- John M. Emmert and Dinesh Bhatia. 1999. Tabu Search: Ultra-fast placement for FPGAs. In FPL. Lecture Notes in Computer Science, Vol. 1673. Springer, New York, NY, 81--90. Google Scholar
Digital Library
- Sonke Hartmann. 2002. A self-adapting genetic algorithm for project scheduling under resource constraints. Naval Research Logistics (NRL) 49, 5, 433--448. DOI: http://dx.doi.org/10.1002/nav.10029Google Scholar
Cross Ref
- Tzung-Pei Hong and Hong-Shung Wang. 1996. A dynamic mutation genetic algorithm. In Proceedings of the 1996 International Conference on Systems, Man, and Cybernetics, Vol. 3. 2000--2005.Google Scholar
- ITRS. 2012. International Technology Roadmap for Semiconductors. Retrieved from http://www.itrs.net/.Google Scholar
- Peter Jamieson. 2010. Revisiting genetic algorithms for the FPGA placement problem. In GEM. 16--22.Google Scholar
- V. Kalenteridis, H. Pournara, K. Siozos, K. Tatas, N. Vassiliadis, I. Pappas, G. Koutroumpezis, S. Nikolaidis, S. Siskos, D. J. Soudris, and A. Thanailakis. 2005. A complete platform and toolset for system implementation on fine-grain reconfigurable hardware. Microprocess. Microsyst. 29, 6, 247--259. DOI: http://dx.doi.org/10.1016/j.micpro.2004.09.001Google Scholar
Cross Ref
- Tapas Kanungo, D. M. Mount, N. S. Netanyahu, C. D. Piatko, R. Silverman, and A. Y. Wu. 2002. An efficient k-means clustering algorithm: analysis and implementation. IEEE Trans. Pattern Anal. Mach. Intell. 24, 7 (2002), 881--892. Google Scholar
Digital Library
- Saul A. Kravitz and Rob A. Rutenbar. 1987. Placement by simulated annealing on a multiprocessor. IEEE Trans. CAD of Integr. Circuits Syst. 6, 4 (1987), 534--549. Google Scholar
Digital Library
- Julien Lamoureux and Steven J. E. Wilton. 2003. On the interaction between power-aware FPGA CAD algorithms. In Proceedings of the 2003 IEEE/ACM International Conference on Computer-Aided Design. 701--708. Google Scholar
Digital Library
- A. Livnat, C. Papadimitriou, J. Dushoff, and M. Feldman. 2008. A mixability theory for the role of sex in evolution. Proc. Natl. Acad. Sci. USA 105, 50 (2008), 19803--19808.Google Scholar
Cross Ref
- Adrian Ludwin and Vaughn Betz. 2011. Efficient and deterministic parallel placement for FPGAs. ACM Trans. Design Autom. Electr. Syst. 16, 3, 22. Google Scholar
Digital Library
- Adrian Ludwin, Vaughn Betz, and Ketan Padalia. 2008. High-quality, deterministic parallel placement for FPGAs on commodity hardware. In FPGA. ACM, New York, NY, 14--23. Google Scholar
Digital Library
- P. Moscato and J. F. Fontanari. 1990. Convergence and finite-time behavior of simulated annealing. Adv. Appl. Probab. 18 (1990), 747--771.Google Scholar
- Edmund M. A. Ronald. 1995. When selection meets seduction. In Proceedings of the 6th International Conference on Genetic Algorithms. Morgan Kaufmann, Philadelphia, PA, 167--173. Google Scholar
Digital Library
- Jonathan Rose, W. Martin Snelgrove, and Zvonko G. Vranesic. 1988. Parallel standard cell placement algorithms with quality equivalent to simulated annealing. IEEE Trans. CAD of Integr Circuits Syst 7, 3, 387--396. Google Scholar
Digital Library
- Yaska Sankar and Jonathan Rose. 1999. Trading quality for compile time: ultra-fast placement for FPGAs. In FPGA. 157--166. Google Scholar
Digital Library
- N. Selvakkumaran and G. Karypis. 2003. Multi-objective hypergraph partitioning algorithms for cut and maximum subdomain degree minimization. In Proceedings of the International Conference on Computer Aided Design (ICCAD’03). 726--733. Google Scholar
Digital Library
- E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, Robert K. Brayton, and Alberto L. Sangiovanni-Vincentelli. 1992. SIS: A System for Sequential Circuit Synthesis. Technical Report No. UCB/ERL M92/41, University of California, Berkeley, CA.Google Scholar
- Donald Shepard. 1968. A two-dimensional interpolation function for irregularly-spaced data. In Proceedings of the 1968 23rd ACM National Conference (ACM’68). 517--524. Google Scholar
Digital Library
- H. Sidiropoulos, K. Siozios, P. Figuli, D. Soudris, and M. Hubner. 2012. On supporting efficient partial reconfiguration with just-in-time compilation. In Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum. 328--335. Google Scholar
Digital Library
- H. Sidiropoulos, K. Siozios, and D. Soudris. 2011. A methodology and tool framework for supporting rapid exploration of memory hierarchies in FPGAs. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’11). 238--243. DOI: http://dx.doi.org/10.1109/FPL.2011.110 Google Scholar
Digital Library
- G. Smecher, S. Wilton, and G. G. F. Lemieux. 2009. Self-hosted placement for massively parallel processor arrays. In Proceedings of the International Conference on Field-Programmable Technology (FPT’09). 159--166. DOI: http://dx.doi.org/10.1109/FPT.2009.5377668Google Scholar
Cross Ref
- R. E. Smith and Claudio Bonacina. 2003. Mating restriction and niching pressure: Results from agents and implications for general EC. In Proc. of the Genetic and Evolutionary Computation Conf. Lecture Notes in Computer Science, Vol. 2724. Springer-Verlag, 1382--1393. Google Scholar
Digital Library
- M. Srinivas and Lalit M. Patnaik. 1994. Adaptive probabilities of crossover and mutation in genetic algorithms. IEEE Trans. Syst. Man Cybern. 24, 4, 656--667.Google Scholar
Cross Ref
- Russell Tessier. 2002. Fast placement approaches for FPGAs. ACM Trans. Design Autom. Electr. Syst. 7, 2 (2002), 284--305. Google Scholar
Digital Library
- Chuan-Kang Ting, Sheng-Tun Li, and Chungnan Lee. 2003. On the harmonious mating strategy through tabu search. Inf. Sci. 156, 3--4 (2003), 189--214. Google Scholar
Digital Library
- Chris C. Wang and Guy G. Lemieux. 2011. Scalable and deterministic timing-driven parallel placement for FPGAs. In FPGA. 153--162. Google Scholar
Digital Library
- Ellen E. Witte, Roger D. Chamberlain, and Mark A. Franklin. 1991. Parallel simulated annealing using speculative computation. IEEE Trans. Parallel Distrib. Syst. 2, 4 (1991), 483--494. Google Scholar
Digital Library
- Michael G. Wrighton and Andr M. Dehon. 2003. Hardware-assisted simulated annealing with application for fast FPGA placement. In Proceedings of the International Symposium on Field-Programmable Gate Arrays. ACM Press, New York, NY, 33--42. Google Scholar
Digital Library
- S. Xydis, A. Bartzas, I. Anagnostopoulos, D. Soudris, and K. Pekmestzi. 2010. Custom multi-threaded dynamic memory management for multiprocessor system-on-chip platforms. Embedded Computer Systems (SAMOS), 2010 International Conference on. IEEE, 102--109. DOI:10.1109/ICSAMOS.2010.5642078Google Scholar
- Vittorio Zaccaria, Gianluca Palermo, Fabrizio Castro, Cristina Silvano, and Giovanni Mariani. 2010. Multicube Explorer: an open source framework for design space exploration of chip multi-processors. In Proceedings of the ARCS Workshops. 325--331.Google Scholar
Index Terms
GENESIS: Parallel Application Placement onto Reconfigurable Architectures (Invited for the Special Issue on Runtime Management)
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