Abstract
With the rapid growth of complex hardware features, timing analysis has become an increasingly difficult problem. The key to solving this problem lies in the precise and scalable modeling of performance-enhancing processor features (e.g., cache). Moreover, real-time systems are often multitasking and use preemptive scheduling, with fixed or dynamic priority assignment. For such systems, cache related preemption delay (CRPD) may increase the execution time of a task. Therefore, CRPD may affect the overall schedulability analysis. Existing works propose to bound the value of CRPD in a single-level cache. In this article, we propose a CRPD analysis framework that can be used for a two-level, noninclusive cache hierarchy. In addition, our proposed framework is also applicable in the presence of shared caches. We first show that CRPD analysis faces several new challenges in the presence of a multilevel, noninclusive cache hierarchy. Our proposed framework overcomes all such challenges and we can formally prove the correctness of our framework. We have performed experiments with several subject programs, including an unmanned aerial vehicle (UAV) controller and an in-situ space debris monitoring instrument. Our experimental results suggest that we can provide sound and precise CRPD estimates using our framework.
- S. Altmeyer and C. Burguiere. 2009. A new notion of useful cache block to improve the bounds of cache-related preemption delay. In Proceedings of the 21st Euromicro Conference on Real-Time Systems (ECRTS'09). 109--118. Google Scholar
Digital Library
- S. Altmeyer, C. Maiza, and J. Reineke. 2010. Resilience analysis: Tightening the crpd bound for set-associative caches. In Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'10). 153--162. Google Scholar
Digital Library
- T. Austin, E. Larson, and D. Ernst. 2002. Simplescalar: An infrastructure for computer system modeling. Comput. 35, 2, 59--67. Google Scholar
Digital Library
- G. Balakrishnan and T. W. Reps. 2004. Analyzing memory accesses in x86 executables. In Proceedings of the 13th International Conference on Compiler Construction, Held as Part of the Joint European Conferences on Theory and Practice of Software (ETAPS'04). 5--23.Google Scholar
- S. Chattopadhyay, L. K. Chong, A. Roychoudhury, T. Kelter, P. Marwedel, and H. Falk. 2012. A unified wcet analysis framework for multi-core platforms. In Proceedings of the 18th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'12). Google Scholar
Digital Library
- S. Chattopadhyay, A. Roychoudhury, and T. Mitra. 2010. Modeling shared cache and bus in multi-cores for timing analysis. In Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems (SCOPES'10). Google Scholar
Digital Library
- Freescale. 2008. i.MX31 applications processor. http://www.freescale.com/files/32bit/doc/data_sheet/MCIMX31.pdf.Google Scholar
- J. Gustafsson, A. Betts, A. Ermedahl, and B. Lisper. 2010. The malardalen wcet benchmarks -- Past, present and future. In Proceedings of the 10th International Workshop on Worst-Case Execution Time Analysis (WCET'10).Google Scholar
- D. Hardy, T. Piquet, and I. Puaut. 2009. Using bypass to tighten wcet estimates for multi-core processors with shared instruction caches. In Proceedings of the 30th IEEE Real-Time Systems Symposium (RTSS'09). Google Scholar
Digital Library
- D. Hardy and I. Puaut. 2008. WCET analysis of multi-level non-inclusive set-associative instruction caches. In Proceedings of the Real-Time Systems Symposium (RTSS'08). Google Scholar
Digital Library
- B. K. Huynh, L. Ju, and A. Roychoudhury. 2011. Scope-aware data cache analysis for wcet estimation. In Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'11). Google Scholar
Digital Library
- J. Kuitunen, G. Drolshagen, J. Mcdonnell, H. Svedhem, M. Leese, H. Mannermaa, M. Kaip Iainen, and V. Sipinen. 2001. DEBIE-First standard in-situ debris monitoring instrument. In Proceedings of the 3rd European Conference on Space Debris. European Space Agency-Publications-Esa, SP 473.Google Scholar
- C.-G. Lee, J. Hahn, Y.-M. Seo, S. L. Min, R. Ha, S. Hong, C. Y. Park, M. Lee, and C. S. Kim. 1998. Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. IEEE Trans. Comput. 47, 6. Google Scholar
Digital Library
- X. Li, Y. Liang, T. Mitra, and A. Roychoudhury. 2007. Chronos: A timing analyzer for embedded software. http://www.comp.nus.edu.sg/rpembed/chronos.Google Scholar
- Y. Li, V. Suhendra, Y. Liang, T. Mitra, and A. Roychoudhury. 2009. Timing analysis of concurrent programs running on shared cache multi-cores. Real-Time Syst. 48, 6, 638--680. Google Scholar
Digital Library
- H. S. Negi, T. Mitra, and A. Roychoudhury. 2003. Accurate estimation of cache-related preemption delay. In Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'03). Google Scholar
Digital Library
- F. Nemer, H. Casse, P. Sainrat, J. Bahsoun, and M. De MICHIEL. 2006. Papabench: A free real-time benchmark. In Proceedings of the Workshop on Worst Case Execution Time (WCET'06).Google Scholar
- J. Staschulat and R. Ernst. 2004. Multiple process execution in cache related preemption delay analysis. In Proceedings of the 4th ACM International Conference on Embedded Software (EMSOFT'04). Google Scholar
Digital Library
- Y. Tan and V. Mooney. 2004. Integrated intra- and inter-task cache analysis for preemptive multi-tasking real-time systems. In Proceedings of the 8th International Workshop on Software and Compilers for Embedded Systems (SCOPES'04).Google Scholar
- H. Theiling, C. Ferdinand, and R. Wilhelm. 2000. Fast and precise wcet prediction by separated cache and path analyses. Real-Time Syst. 18, 3. Google Scholar
Digital Library
- H. Tomiyama and N. D. Dutt. 2000. Program path analysis to bound cache-related preemption delay in preemptive real-time systems. In Proceedings of the 8th International Workshop on Hardware/Software Codesign (CODES'00). Google Scholar
Digital Library
- J. Yan and W. Zhang. 2008. WCET analysis for multi-core processors with shared l2 instruction caches. In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'08). Google Scholar
Digital Library
- M. M. Zahran, K. Albayraktaroglu, and M. Franklin. 2007. Non-inclusion property in multi-level caches revisited. Int. J. Comput. Appl. 14, 2.Google Scholar
Index Terms
Cache-Related Preemption Delay Analysis for Multilevel Noninclusive Caches
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