Abstract
Dependability issues due to nonfunctional properties are emerging as a major cause of faults in modern digital systems. Effective countermeasures have to be developed to properly manage their critical timing effects. This article presents a methodology to avoid transition delay faults in field-programmable gate array (FPGA)-based systems, with low area overhead. The approach is able to exploit temperature information and aging characteristics to minimize the cost in terms of performances degradation and power consumption. The architecture of a hardware manager able to avoid delay faults is presented and analyzed extensively, as well as its integration in the standard implementation design flow.
- Altera Corporation. 2012. Stratix V Device Overview (sv51001 ed.).Google Scholar
- Altera Corporation. 2013. The Breakthrough Advantage for FPGAs with Tri-Gate Technology (wp435wp-01201-1.0 ed.).Google Scholar
- A. Amouri and M. Tahoori. 2011. A low-cost sensor for aging and late transitions detection in modern FPGAs. In Proceedings of the 2011 International Conference on Field Programmable Logic and Applications (FPL’11). 329--335. DOI: http://dx.doi.org/10.1109/FPL.2011.66 Google Scholar
Digital Library
- A. Amouri and M. Tahoori. 2012. High-level aging estimation for FPGA-mapped designs. In Proceedings of the 2012 22nd International Conference on Field Programmable Logic and Applications (FPL’12). 284--291. DOI: http://dx.doi.org/10.1109/FPL.2012.6339194Google Scholar
- V. Bexiga, C. Leong, J. Semiao, I. C. Teixeira, J. P. Teixeira, M. Valdes, J. Freijedo, J. J. Rodriguez-Andina, and F. Vargas. 2011. Performance failure prediction using built-in delay sensors in FPGAs. In Proceedings of the 2011 International Conference on Field Programmable Logic and Applications (FPL’11). 301--304. DOI: http://dx.doi.org/10.1109/FPL.2011.61 Google Scholar
Digital Library
- Jung-Hwan Choi, Jayathi Murthy, and K. Roy. 2007. The effect of process variation on device temperature in finFET circuits. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD’07). 747--751. DOI: http://dx.doi.org/10.1109/ICCAD.2007.4397355 Google Scholar
Digital Library
- S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner, and T. Mudge. 2006. A self-tuning DVS processor using delay-error detection and correction. IEEE Journal of Solid-State Circuits 41, 4, 792--804. DOI: http://dx.doi.org/10.1109/JSSC.2006.870912Google Scholar
Cross Ref
- S. Das, C. Tokunaga, S. Pant, W.-H. Ma, S. Kalaiselvan, K. Lai, D. M. Bull, and D. T. Blaauw. 2009. RazorII: In situ error detection and correction for PVT and SER tolerance. IEEE Journal of Solid-State Circuits 44, 1, 32--48. DOI: http://dx.doi.org/10.1109/JSSC.2008.2007145Google Scholar
Cross Ref
- S. Di Carlo, S. Galfano, G. Gambardella, D. Rolfo, P. Prinetto, and P. Trotta. 2012. NBTI Mitigation by dynamic partial reconfiguration. In Proceedings of the 2012 13th Biennial Baltic Electronics Conference (BEC’12). 93--96. DOI: http://dx.doi.org/10.1109/BEC.2012.6376823Google Scholar
Cross Ref
- M. Fukazawa, M. Kurimoto, R. Akiyama, H. Takata, and Makoto Nagata. 2008. Experimental evaluation of digital-circuit susceptibility to voltage variation in dynamic frequency scaling. In Proceedings of the 2008 IEEE Symposium on VLSI Circuits. 150--151. DOI: http://dx.doi.org/10.1109/VLSIC.2008.4585986Google Scholar
Cross Ref
- H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye. 2012. Adaptive performance compensation with in-situ timing error predictive sensors for subthreshold circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, 2, 333--343. DOI: http://dx.doi.org/10.1109/TVLSI.2010.2101089 Google Scholar
Digital Library
- J. Gaisler. 2002. A portable and fault-tolerant microprocessor based on the SPARC v8 architecture. In Proceedings of the 2002 International Conferenc on Dependable Systems and Networks (DSN’02). 409--415. DOI: http://dx.doi.org/10.1109/DSN.2002.1028926 Google Scholar
Digital Library
- M. Happe, A. Agne, and C. Plessl. 2011. Measuring and predicting temperature distributions on FPGAs at run-time. In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig’11). 55--60. DOI: http://dx.doi.org/10.1109/ReConFig.2011.59 Google Scholar
Digital Library
- T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye. 2012. A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture. In Proceedings of the 2012 22nd International Conference on Field Programmable Logic and Applications (FPL’12). 615--618. DOI: http://dx.doi.org/10.1109/FPL.2012.6339220Google Scholar
- J. Li and J. Lach. 2007. Negative-skewed shadow registers for at-speed delay variation characterization. In Proceedings of the 25th International Conference on Computer Design (ICCD’07). 354--359. DOI: http://dx.doi.org/10.1109/ICCD.2007.4601924Google Scholar
- OpenCores. 2009. AES (Rijndael). Retrieved from http://opencores.org/project,rijndael.Google Scholar
- OpenCores. 2013. Amber ARM-compatible core. Retrieved from http://opencores.org/project,amber.Google Scholar
- S. P. Park, K. Kang, and K. Roy. 2009. Reliability implications of bias-temperature instability in digital ICs. IEEE Design & Test of Computers 26, 6, 8--17. DOI: http://dx.doi.org/10.1109/MDT.2009.154 Google Scholar
Digital Library
- P. Pfeifer and Z. Pliva. 2012. On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults. In Proceedings of the 2012 22nd International Conference on Field Programmable Logic and Applications (FPL’12). 743--746. DOI: http://dx.doi.org/10.1109/FPL.2012.6339167Google Scholar
- P. Pfeifer and Z. Pliva. 2013. On measurement of parameters of programmable microelectronic nanostructures under accelerating extreme conditions (Xilinx 28nm XC7Z020 Zynq FPGA). In Proceedings of the 2013 23rd International Conference on Field Programmable Logic and Applications (FPL’13). 1--4. DOI: http://dx.doi.org/10.1109/FPL.2013.6645584Google Scholar
Cross Ref
- T. Sato and Y. Kunitake. 2007. A simple flip-flop circuit for typical-case designs for DFM. In Proceedings of the 8th International Symposium on Quality Electronic Design (ISQED’07). 539--544. DOI: http://dx.doi.org/10.1109/ISQED.2007.23 Google Scholar
Digital Library
- S. Srinivasan, R. Krishnan, P. Mangalagiri, Y. Xie, V. Narayanan, M. J. Irwin, and K. Sarpatwari. 2008. Toward increasing FPGA lifetime. IEEE Transactions on Dependable and Secure Computing 5, 2, 115--127. DOI: http://dx.doi.org/10.1109/TDSC.2007.70235 Google Scholar
Digital Library
- E. A. Stott, J. S. J. Wong, P. Sedcole, and P. Y. K. Cheung. 2010. Degradation in FPGAs: Measurement and modelling. In Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA’10). ACM, New York, NY, 229--238. DOI: http://dx.doi.org/10.1145/1723112.1723152 Google Scholar
Digital Library
- M. D. Valdes-Pena, J. Fernandez Freijedo, M. J. M. Rodriguez, J. J. Rodriguez-Andina, J. Semiao, I. M. Cacho Teixeira, J. P. Cacho Teixeira, and F. Vargas. 2013. Design and validation of configurable online aging sensors in nanometer-scale FPGAs. IEEE Transactions on Nanotechnology 12, 4, 508--517. DOI: http://dx.doi.org/10.1109/TNANO.2013.2253795 Google Scholar
Digital Library
- Xilinx Corporation. 2012. 7 Series FPGAs Overview (ds180 (v1.14) ed.).Google Scholar
- Xilinx Corporation. 2013a. 7 Series FPGAs Clocking Resources (ug472 (v1.8) ed.).Google Scholar
- Xilinx Corporation. 2013b. 7 Series FPGAs Configurable Logic Block (ug474 (v1.5) ed.).Google Scholar
- Xilinx Corporation. 2013c. Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture (wp435 ed.).Google Scholar
- K. M. Zick and J. P. Hayes. 2010. On-line sensing for healthier FPGA systems. In Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA’10). ACM, New York, NY, 239--248. DOI: http://dx.doi.org/10.1145/1723112.1723153 Google Scholar
Digital Library
Index Terms
SATTA: A Self-Adaptive Temperature-Based TDF Awareness Methodology for Dynamically Reconfigurable FPGAs
Recommendations
High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal Processing
DSD '12: Proceedings of the 2012 15th Euromicro Conference on Digital System DesignThe use of Field Programmable Gate Array (FPGA) based System on Chip (SoC) is a promising approach in Multimedia applications. In SoC, computationally intensive tasks are off-loaded to the hardware logic. A feature introduced with new FPGA devices, ...
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems
The growth of the Reconfigurable Computing (RC) systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Low-level design tools are increasingly required for RC bitstream debugging and IP ...
Secure Extension of FPGA General Purpose Processors for Symmetric Key Cryptography with Partial Reconfiguration Capabilities
In data security systems, general purpose processors (GPPs) are often extended by a cryptographic accelerator. The article presents three ways of extending GPPs for symmetric key cryptography applications. Proposed extensions guarantee secure key ...






Comments