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Partitioning data-parallel programs for heterogeneous MPSoCs: time and energy design space exploration

Published:12 June 2014Publication History
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Abstract

Multiprocessor System-on-Chips(MPSoCs) are now widely used in embedded devices. MPSoCs typically contain a range of specialised processors. Alongside the CPU, there are microcontrollers, DSPs and other hardware accelerators. Programming these MPSoCs is difficult because of the difference in instruction-set architecture (ISA) and disjoint address spaces. In this paper we consider MPSoCs as a target for individual benchmarks. We examine how data-parallel programs can be optimally mapped to heterogeneous multicores for different criteria such as performance, power and energy. We investigate the partitioning of seven benchmarks taken from DSPstone, UTDSP and Polybench suites. Based on design space exploration we show that the best partition depends on compiler optimization level, program, input size and crucially optimization criteria. We develop a straightforward approach that attempts to select the best partitioning for a given program. On average it achieves speedups of 2.2x and energy improvements of 1.45x on the OMAP 4430 platform.

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    • Published in

      cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 49, Issue 5
      LCTES '14
      May 2014
      162 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/2666357
      Issue’s Table of Contents
      • cover image ACM Conferences
        LCTES '14: Proceedings of the 2014 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
        June 2014
        174 pages
        ISBN:9781450328777
        DOI:10.1145/2597809

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      • Published: 12 June 2014

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