Abstract
With increasing complexity and software content, modern embedded platforms employ a heterogeneous mix of multicore processors along with hardware accelerators in order to provide high performance in limited power budgets. To evaluate real-time performance and other constraints, full system simulations are essential. With traditional approaches being either slow or inaccurate, so-called source-level or host-compiled simulators have recently emerged as a solution for rapid evaluation of the complete system at early design stages. In such approaches, a faster simulation is achieved by abstracting execution behavior and increasing simulation granularity. However, existing source-level simulators often focus on application behavior only while neglecting the effects of hardware/software interactions and their associated speed and accuracy trade-offs.
In this article, we present a host-compiled simulator that emulates software execution in a full-system context. Our simulator incorporates abstract models of both real-time operating systems (RTOSs) and multicore processors to replicate timing-accurate hardware/software interactions and to enable full system cosimulation. An integrated approach for automatic timing granularity adjustment (ATGA) uses observations of the system state to automatically control the timing model and optimally navigate speed versus accuracy conditions. Results as applied to industrial-strength platforms confirm that OS- and system-level effects can significantly contribute to overall accuracy and simulation overhead. By providing careful abstractions, our models can achieve full system simulations at equivalent speeds of more than a thousand MIPS with less than 3% timing error. Coupled with the capability to easily adjust simulation parameters and configurations, this demonstrates the benefits of our simulator for early application development and design space exploration.
- ARM. 2014. ARM generic interrupt controller architecture specification. http://infocenter.arm.com.Google Scholar
- T. Austin, E. Larson, and D. Ernst. 2002. SimpleScalar: An infrastructure for computer system modeling. Comput. 35, 2, 59--67. Google Scholar
Digital Library
- F. Bellard. 2005. QEMU, a fast and portable dynamic translator. In Proceedings of the USENIX Annual Technical Conference (ATEC'05). Google Scholar
Digital Library
- L. Benini, D. Bertozzi, A. Bogliolo, F. Menichelli, and M. Olivieri. 2005. MPARM: Exploring the multi-processor soc design space with systemc. J. VLSI Signal Process. Syst. Signal Image Video Technol. 41, 2, 169--182. Google Scholar
Digital Library
- N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood. 2011. The gem5 simulator. SIGARCH Comput. Archit. News 39, 2, 1--7. Google Scholar
Digital Library
- G. Blake, R. G. Dreslinski, and T. Mudge. 2009. A survey of multicore processors. IEEE Signal Process. Mag. 26, 26--37.Google Scholar
Cross Ref
- A. Bouchhima, P. Gerin, and F. Petrot. 2009. Automatic instrumentation of embedded software for high level hardware/software co-simulation. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'09). Google Scholar
Digital Library
- L. Cai and D. Gajski. 2003. Transaction level modeling: An overview. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'03). Google Scholar
Digital Library
- J. Ceng, W. Sheng, J. Castrillon, A. Stulova, R. Leupers, G. Ascheid, and H. Meyr. 2009. A high-level virtual platform for early mpsoc software development. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'09). Google Scholar
Digital Library
- D. D. Gajski, J. Zhu, R. Domer, A. Gerstlauer, and S. Zhao. 2000. SpecC: Specification Language and Methodology. Springer.Google Scholar
- P. Gerin, H. Shen, A. Chureau, A. Bouchhima, and A. Jerraya. 2007. Flexible and executable hardware/software interface modeling for multiprocessor soc design using systemc. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'07). Google Scholar
Digital Library
- A. Gerstlauer. 2010. Host-compiled simulation of multi-core platforms. In Proceedings of the International Symposium on Rapid System Prototyping (RSP'10).Google Scholar
Cross Ref
- A. Gerstlauer, H. Yu, and D. Gajski. 2003. RTOS modeling for system level design. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'03). Google Scholar
Digital Library
- F. Ghenassia. 2005. Transaction Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems. Springer. Google Scholar
Digital Library
- HCSIM-1.0. 2014. http://www.ece.utexas.edu/∼gerstl/releases.Google Scholar
- Y. Hwang, S. Abdi, and D. Gajski. 2008. Cycle-approximate retargetable performance estimation at the transaction level. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'08). Google Scholar
Digital Library
- IMPERAS. 2014. Imperas software limited. http://www.imperas.com.Google Scholar
- S. Iqbal, Y. Liang, and H. Grahn. 2010. ParMiBench - An open-source benchmark for embedded multiprocessor systems. Comput. Archit. Lett. 9, 2, 45--48. Google Scholar
Digital Library
- M. Krause, D. Englert, O. Bringmann, and W. Rosenstiel. 2008. Combination of instruction set simulation and abstract rtos model execution for fast and accurate target software evaluation. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'08). Google Scholar
Digital Library
- S. Lauzac, R. G. Melhem, and D. Mosse. 1998. Comparison of global and partitioning schemes for scheduling rate monotonic tasks on a multiprocessor. In Proceedings of the 10th EuroMicro Workshop on Real-Time Systems (EMWRTS'98).Google Scholar
- K.-L. Lin, C.-K. Lo, and R.-S. Tsay. 2010. Source-level timing annotation for fast and accurate tlm computation model generation. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'10). Google Scholar
Digital Library
- P. S. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, F. Larsson, A. Moestedt, and B. Werner. 2002. Simics: A full system simulation platform. Comput. 35, 2, 50--58. Google Scholar
Digital Library
- T. Meyerowitz, A. Sangiovanni-Vincentelli, M. Sauermann, and D. Langen. 2008. Source-level timing annotation and simulation for a heterogeneous multiprocessor. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'08). Google Scholar
Digital Library
- B. Miramond, E. Huck, F. Verdier, M. E. A. Benkhelifa, B. Granado, T. Lefebvre, M. Aichouch, J.-C. Prvotet, Y. Oliva, D. Chillet, and S. Pillement. 2009. OveRSoC: A framework for the exploration of RTOS for RSOC platforms. Int. J. Reconfigur. Comput. 2009. Google Scholar
Digital Library
- OVP. 2014. Open virtual platforms. http://www.ovpworld.org.Google Scholar
- H. Posadas, J. Damez, E. Villar, F. Blasco, and F. Escuder. 2005. RTOS modeling in systemc for real-time embedded SW simulation: A posix model. Des. Autom. Embedd. Syst. 10, 4, 209--227. Google Scholar
Digital Library
- P. Razaghi and A. Gerstlauer. 2011. Host-compiled multicore RTOS simulator for embedded real-time software development. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'11).Google Scholar
- P. Razaghi and A. Gerstlauer. 2012a. Automatic timing granularity adjustment for host-compiled software simulation. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'12).Google Scholar
- P. Razaghi and A. Gerstlauer. 2012b. Predictive os modeling for host-compiled simulation of periodic real-time task sets. IEEE Embedd. Syst. Lett. 4, 1. Google Scholar
Digital Library
- P. Razaghi and A. Gerstlauer. 2013. Multi-core cache hierarchy modeling for host-compiled performance simulation. In Proceedings of the Electronic System Level Synthesis Conference (ESLSyn'13).Google Scholar
- J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, and P. Montesinos. 2005. SESC simulator. http://sesc.sourceforge.net.Google Scholar
- R. Salimi Khaligh and M. Radetzki. 2010. Modeling constructs and kernel for parallel simulation of accuracy adaptive tlms. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'10). Google Scholar
Digital Library
- G. Schirner and R. Domer. 2008. Introducing preemptive scheduling in abstract RTOS models using result oriented modeling. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'08). Google Scholar
Digital Library
- G. Schirner and R. Domer. 2009. Quantitative analysis of the speed/accuracy trade-off in transaction level modeling. ACM Trans. Embedd. Comput. Syst. 8, 1, 4:1--4:29. Google Scholar
Digital Library
- G. Schirner, A. Gerstlauer, and R. Domer. 2010. Fast and accurate processor models for efficient MPSOC design. ACM Trans. Des. Autom. Electron. Syst. 15, 2, 10:1--10:26. Google Scholar
Digital Library
- J. Schnerr, O. Bringmann, and W. Rosenstiel. 2005. Cycle accurate binary translation for simulation acceleration in rapid prototyping of socs. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'05). Google Scholar
Digital Library
- J. Schnerr, O. Bringmann, A. Viehl, and W. Rosenstiel. 2008. High-performance timing simulation of embedded software. In Proceedings of the Design Automation Conference (DAC'08). Google Scholar
Digital Library
- S. Stattelmann, O. Bringmann, and W. Rosenstiel. 2011. Fast and accurate resource conflict simulation for performance analysis of multi-core systems. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'11).Google Scholar
- Z. Wang and J. Henkel. 2012. Accurate source-level simulation of embedded software with respect to compiler optimizations. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'12). Google Scholar
Digital Library
Index Terms
Host-Compiled Multicore System Simulation for Early Real-Time Performance Evaluation
Recommendations
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
DAC '03: Proceedings of the 40th annual Design Automation ConferenceInstruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and time-to-market pressure, performance is the most important feature of an ...
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation
Instruction-set simulators are critical tools for the exploration and validation of new processor architectures. Due to the increasing complexity of architectures and time-to-market pressure, performance is the most important feature of an instruction-...
Predictive OS Modeling for Host-Compiled Simulation of Periodic Real-Time Task Sets
With the increasing complexity of embedded software, host-compiled simulators have been introduced to address the need for a fast simulation environment. However, designers pay the price for higher performance with a loss in timing accuracy. In this ...






Comments