skip to main content
research-article

Host-Compiled Multicore System Simulation for Early Real-Time Performance Evaluation

Published:15 December 2014Publication History
Skip Abstract Section

Abstract

With increasing complexity and software content, modern embedded platforms employ a heterogeneous mix of multicore processors along with hardware accelerators in order to provide high performance in limited power budgets. To evaluate real-time performance and other constraints, full system simulations are essential. With traditional approaches being either slow or inaccurate, so-called source-level or host-compiled simulators have recently emerged as a solution for rapid evaluation of the complete system at early design stages. In such approaches, a faster simulation is achieved by abstracting execution behavior and increasing simulation granularity. However, existing source-level simulators often focus on application behavior only while neglecting the effects of hardware/software interactions and their associated speed and accuracy trade-offs.

In this article, we present a host-compiled simulator that emulates software execution in a full-system context. Our simulator incorporates abstract models of both real-time operating systems (RTOSs) and multicore processors to replicate timing-accurate hardware/software interactions and to enable full system cosimulation. An integrated approach for automatic timing granularity adjustment (ATGA) uses observations of the system state to automatically control the timing model and optimally navigate speed versus accuracy conditions. Results as applied to industrial-strength platforms confirm that OS- and system-level effects can significantly contribute to overall accuracy and simulation overhead. By providing careful abstractions, our models can achieve full system simulations at equivalent speeds of more than a thousand MIPS with less than 3% timing error. Coupled with the capability to easily adjust simulation parameters and configurations, this demonstrates the benefits of our simulator for early application development and design space exploration.

References

  1. ARM. 2014. ARM generic interrupt controller architecture specification. http://infocenter.arm.com.Google ScholarGoogle Scholar
  2. T. Austin, E. Larson, and D. Ernst. 2002. SimpleScalar: An infrastructure for computer system modeling. Comput. 35, 2, 59--67. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. F. Bellard. 2005. QEMU, a fast and portable dynamic translator. In Proceedings of the USENIX Annual Technical Conference (ATEC'05). Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. L. Benini, D. Bertozzi, A. Bogliolo, F. Menichelli, and M. Olivieri. 2005. MPARM: Exploring the multi-processor soc design space with systemc. J. VLSI Signal Process. Syst. Signal Image Video Technol. 41, 2, 169--182. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood. 2011. The gem5 simulator. SIGARCH Comput. Archit. News 39, 2, 1--7. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. G. Blake, R. G. Dreslinski, and T. Mudge. 2009. A survey of multicore processors. IEEE Signal Process. Mag. 26, 26--37.Google ScholarGoogle ScholarCross RefCross Ref
  7. A. Bouchhima, P. Gerin, and F. Petrot. 2009. Automatic instrumentation of embedded software for high level hardware/software co-simulation. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'09). Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. L. Cai and D. Gajski. 2003. Transaction level modeling: An overview. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'03). Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. J. Ceng, W. Sheng, J. Castrillon, A. Stulova, R. Leupers, G. Ascheid, and H. Meyr. 2009. A high-level virtual platform for early mpsoc software development. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'09). Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. D. D. Gajski, J. Zhu, R. Domer, A. Gerstlauer, and S. Zhao. 2000. SpecC: Specification Language and Methodology. Springer.Google ScholarGoogle Scholar
  11. P. Gerin, H. Shen, A. Chureau, A. Bouchhima, and A. Jerraya. 2007. Flexible and executable hardware/software interface modeling for multiprocessor soc design using systemc. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'07). Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. A. Gerstlauer. 2010. Host-compiled simulation of multi-core platforms. In Proceedings of the International Symposium on Rapid System Prototyping (RSP'10).Google ScholarGoogle ScholarCross RefCross Ref
  13. A. Gerstlauer, H. Yu, and D. Gajski. 2003. RTOS modeling for system level design. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'03). Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. F. Ghenassia. 2005. Transaction Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems. Springer. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. HCSIM-1.0. 2014. http://www.ece.utexas.edu/∼gerstl/releases.Google ScholarGoogle Scholar
  16. Y. Hwang, S. Abdi, and D. Gajski. 2008. Cycle-approximate retargetable performance estimation at the transaction level. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'08). Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. IMPERAS. 2014. Imperas software limited. http://www.imperas.com.Google ScholarGoogle Scholar
  18. S. Iqbal, Y. Liang, and H. Grahn. 2010. ParMiBench - An open-source benchmark for embedded multiprocessor systems. Comput. Archit. Lett. 9, 2, 45--48. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. M. Krause, D. Englert, O. Bringmann, and W. Rosenstiel. 2008. Combination of instruction set simulation and abstract rtos model execution for fast and accurate target software evaluation. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'08). Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. S. Lauzac, R. G. Melhem, and D. Mosse. 1998. Comparison of global and partitioning schemes for scheduling rate monotonic tasks on a multiprocessor. In Proceedings of the 10th EuroMicro Workshop on Real-Time Systems (EMWRTS'98).Google ScholarGoogle Scholar
  21. K.-L. Lin, C.-K. Lo, and R.-S. Tsay. 2010. Source-level timing annotation for fast and accurate tlm computation model generation. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'10). Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. P. S. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, F. Larsson, A. Moestedt, and B. Werner. 2002. Simics: A full system simulation platform. Comput. 35, 2, 50--58. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. T. Meyerowitz, A. Sangiovanni-Vincentelli, M. Sauermann, and D. Langen. 2008. Source-level timing annotation and simulation for a heterogeneous multiprocessor. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'08). Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. B. Miramond, E. Huck, F. Verdier, M. E. A. Benkhelifa, B. Granado, T. Lefebvre, M. Aichouch, J.-C. Prvotet, Y. Oliva, D. Chillet, and S. Pillement. 2009. OveRSoC: A framework for the exploration of RTOS for RSOC platforms. Int. J. Reconfigur. Comput. 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. OVP. 2014. Open virtual platforms. http://www.ovpworld.org.Google ScholarGoogle Scholar
  26. H. Posadas, J. Damez, E. Villar, F. Blasco, and F. Escuder. 2005. RTOS modeling in systemc for real-time embedded SW simulation: A posix model. Des. Autom. Embedd. Syst. 10, 4, 209--227. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. P. Razaghi and A. Gerstlauer. 2011. Host-compiled multicore RTOS simulator for embedded real-time software development. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'11).Google ScholarGoogle Scholar
  28. P. Razaghi and A. Gerstlauer. 2012a. Automatic timing granularity adjustment for host-compiled software simulation. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'12).Google ScholarGoogle Scholar
  29. P. Razaghi and A. Gerstlauer. 2012b. Predictive os modeling for host-compiled simulation of periodic real-time task sets. IEEE Embedd. Syst. Lett. 4, 1. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. P. Razaghi and A. Gerstlauer. 2013. Multi-core cache hierarchy modeling for host-compiled performance simulation. In Proceedings of the Electronic System Level Synthesis Conference (ESLSyn'13).Google ScholarGoogle Scholar
  31. J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, and P. Montesinos. 2005. SESC simulator. http://sesc.sourceforge.net.Google ScholarGoogle Scholar
  32. R. Salimi Khaligh and M. Radetzki. 2010. Modeling constructs and kernel for parallel simulation of accuracy adaptive tlms. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'10). Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. G. Schirner and R. Domer. 2008. Introducing preemptive scheduling in abstract RTOS models using result oriented modeling. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'08). Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. G. Schirner and R. Domer. 2009. Quantitative analysis of the speed/accuracy trade-off in transaction level modeling. ACM Trans. Embedd. Comput. Syst. 8, 1, 4:1--4:29. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. G. Schirner, A. Gerstlauer, and R. Domer. 2010. Fast and accurate processor models for efficient MPSOC design. ACM Trans. Des. Autom. Electron. Syst. 15, 2, 10:1--10:26. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. J. Schnerr, O. Bringmann, and W. Rosenstiel. 2005. Cycle accurate binary translation for simulation acceleration in rapid prototyping of socs. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'05). Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. J. Schnerr, O. Bringmann, A. Viehl, and W. Rosenstiel. 2008. High-performance timing simulation of embedded software. In Proceedings of the Design Automation Conference (DAC'08). Google ScholarGoogle ScholarDigital LibraryDigital Library
  38. S. Stattelmann, O. Bringmann, and W. Rosenstiel. 2011. Fast and accurate resource conflict simulation for performance analysis of multi-core systems. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'11).Google ScholarGoogle Scholar
  39. Z. Wang and J. Henkel. 2012. Accurate source-level simulation of embedded software with respect to compiler optimizations. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'12). Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Host-Compiled Multicore System Simulation for Early Real-Time Performance Evaluation

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in

    Full Access

    • Published in

      cover image ACM Transactions on Embedded Computing Systems
      ACM Transactions on Embedded Computing Systems  Volume 13, Issue 5s
      Special Issue on Risk and Trust in Embedded Critical Systems, Special Issue on Real-Time, Embedded and Cyber-Physical Systems, Special Issue on Virtual Prototyping of Parallel and Embedded Systems (ViPES)
      November 2014
      501 pages
      ISSN:1539-9087
      EISSN:1558-3465
      DOI:10.1145/2660459
      Issue’s Table of Contents

      Copyright © 2014 ACM

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 15 December 2014
      • Accepted: 1 March 2014
      • Revised: 1 December 2013
      • Received: 1 June 2013
      Published in tecs Volume 13, Issue 5s

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • research-article
      • Research
      • Refereed

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader
    About Cookies On This Site

    We use cookies to ensure that we give you the best experience on our website.

    Learn more

    Got it!