Abstract
It is common for large hardware designs to have a number of registers or memories whose contents have to be changed very seldom (e.g., only at startup). The conventional way of accessing these memories is through a low-speed memory bus. This bus uses valuable hardware resources, introduces long global connections, and contributes to routing congestion. Hence, it has an impact on the overall design even though it is only rarely used. A Field-Programmable Gate Array (FPGA) already contains a global communication mechanism in the form of its configuration infrastructure. In this article, we evaluate the use of the configuration infrastructure as a replacement for a low-speed memory bus on the Maxeler HPC platform. We find that by removing the conventional low-speed memory bus, the maximum clock frequency of some applications can be improved by 8%. Improvements by 25% and more are also attainable, but constraints of the Xilinx reconfiguration infrastructure prevent fully exploiting these benefits at the moment. We present a number of possible changes to the Xilinx reconfiguration infrastructure and tools that would solve this and make these results more widely applicable.
- Hari Angepat, Gage Eads, Christopher Craik, and Derek Chiou. 2010. NIFD: Non-intrusive FPGA debugger. 2010 International Conference on Field Programmable Logic and Applications (Aug. 2010), 356--359. Google Scholar
Digital Library
- C. Beckhoff, D. Koch, and J. Torresen. 2012. GoAhead: A partial reconfiguration framework. In IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 37--44. Google Scholar
Digital Library
- Gordon Brebner and Adam Donlin. 1998. Runtime reconfigurable routing. Parallel and Distributed Processing (1998), 25--30.Google Scholar
- Karel Bruneel, Wim Heirman, and Dirk Stroobandt. 2011. Dynamic data folding with parameterizable FPGA configurations. ACM Transactions on Design Automation of Electronic Systems (TODAES) 16, 4 (2011), 43:1--43:29. Google Scholar
Digital Library
- R. Cattaneo, C. Pilato, M. Mastinu, O. Kadlcek, O. Pell, and M. D. Santambrogio. 2013. Runtime adaptation on dataflow HPC platforms. In NASA/ESA Conference on Adaptive Hardware and Systems (AHS). 84--91.Google Scholar
- Andreas Ehliar and Jacob Siverskog. 2011. Using partial reconfigurability to aid debugging of FPGA designs. In 2011 VII Southern Conference on Programmable Logic (SPL). IEEE, 215--220.Google Scholar
Cross Ref
- Karel Heyse, Dirk Stroobandt, Oliver Kadlcek, and Oliver Pell. 2014. On the impact of replacing a low-speed memory bus on the Maxeler platform, using the FPGA’s configuration infrastructure. In Lecture Notes in Computer Science: Reconfigurable Computing: Architectures, Tools, and Applications, Vol. 8405. 85--96.Google Scholar
Cross Ref
- Oliver Pell, Oskar Mencer, Kuen Hung Tsoi, and Wayne Luk. 2013. Maximum performance computing with dataflow engines. High-Performance Computing Using FPGAs (2013), 747--774.Google Scholar
- Oliver Sander, Lars Braun, M. Hübner, and J. Becker. 2008. Data reallocation by exploiting FPGA configuration mechanisms. Reconfigurable Computing: Architectures, Tools and Applications (2008), 312--317. Google Scholar
Digital Library
- M. Shelburne, C. Patterson, P. Athanas, M. Jones, B. Martin, and R. Fong. 2008. MetaWire: Using FPGA configuration circuitry to emulate a network-on-chip. In International Conference on Field Programmable Logic and Applications. 257--262.Google Scholar
- Xilinx. 2007. Difference-based partial reconfiguration. XAPP290 (2007), 1--11. http://www.xilinx.com/support/documentation/application_notes/xapp290.pdf.Google Scholar
- Xilinx. 2010. Partial reconfiguration user guide. UG702 (2010). http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf.Google Scholar
- Xilinx. 2012a. Constraints guide. UG625 (2012). http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/cgd.pdf.Google Scholar
- Xilinx. 2012b. LogiCORE IP AXI HWICAP (v2.03.a). DS817 (2012). http://www.xilinx.com/support/documentation/ip_documentation/axi_hwicap/v2_03_a/ds817_axi_hwicap.pdf.Google Scholar
- Xilinx. 2012c. Virtex-5 FPGA configuration user guide. UG191 (2012). http://www.xilinx.com/support/documentation/user_guides/ug191.pdf.Google Scholar
- Xilinx. 2012d. Virtex-6 FPGA configuration user guide. UG360 (2012). http://www.xilinx.com/support/documentation/user_guides/ug360.pdf.Google Scholar
Index Terms
On the Impact of Replacing Low-Speed Configuration Buses on FPGAs with the Chip’s Internal Configuration Infrastructure
Recommendations
An FPGA implementation for neural networks with the FDFM processor core approach
This paper presents a field programmable gate array FPGA implementation of a three-layer perceptron using the few DSP blocks and few block RAMs FDFM approach implemented in the Xilinx Virtex-6 family FPGA. In the FDFM approach, multiple processor cores ...
High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal Processing
DSD '12: Proceedings of the 2012 15th Euromicro Conference on Digital System DesignThe use of Field Programmable Gate Array (FPGA) based System on Chip (SoC) is a promising approach in Multimedia applications. In SoC, computationally intensive tasks are off-loaded to the hardware logic. A feature introduced with new FPGA devices, ...
Dynamic Partial Reconfiguration in FPGAs for DSP Applications
ICETET '11: Proceedings of the 2011 Fourth International Conference on Emerging Trends in Engineering & TechnologyDSP Application needs to speed-up in computation time can be achieved by assigning complex computation intensive tasks to hardware and by exploiting the parallelism in algorithms.These applications need high performance as well as cost efficient design. ...






Comments