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Parallel real-time garbage collection of multiple heaps in reconfigurable hardware

Published:12 June 2014Publication History
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Abstract

Despite rapid increases in memory capacity, reconfigurable hardware is still programmed in a very low-level manner, generally without any dynamic allocation at all. This limits productivity especially as the larger chips encourage more and more complex designs to be attempted.

Prior work has shown that it is possible to implement a real-time collector in hardware and achieve stall-free operation --- but at the price of severe restrictions on object layouts. We present the first hardware garbage collector capable of collecting multiple inter-connected heaps, thereby allowing a rich set of object types.

We show that for a modest additional cost in logic and memory, we can support multiple heaps at a clock frequency competitive with monolithic, fixed-layout heaps. We evaluate the hardware design by synthesizing it for a Xilinx FPGA and using co-simulation to measure the run-time behavior over a set of four benchmarks. Even at high allocation and mutation rates the collector is able to sustain stall-free (100% minimum mutator utilization) operation with up to 4 inter-connected heaps, while only requiring between 1.1 and 1.7 times the maximum live memory of the application.

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    • Published in

      cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 49, Issue 11
      ISMM '14
      November 2014
      121 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/2775049
      • Editor:
      • Andy Gill
      Issue’s Table of Contents
      • cover image ACM Conferences
        ISMM '14: Proceedings of the 2014 international symposium on Memory management
        June 2014
        136 pages
        ISBN:9781450329217
        DOI:10.1145/2602988

      Copyright © 2014 ACM

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      New York, NY, United States

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      • Published: 12 June 2014

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