skip to main content
research-article

A Calculus for Relaxed Memory

Published:14 January 2015Publication History
Skip Abstract Section

Abstract

We propose a new approach to programming multi-core, relaxed-memory architectures in imperative, portable programming languages. Our memory model is based on explicit, programmer-specified requirements for order of execution and the visibility of writes. The compiler then realizes those requirements in the most efficient manner it can. This is in contrast to existing memory models, which---if they allow programmer control over synchronization at all---are based on inferring the execution and visibility consequences of synchronization operations or annotations in the code.

We formalize our memory model in a core calculus called RMC\@. Outside of the programmer's specified requirements, RMC is designed to be strictly more relaxed than existing architectures. It employs an aggressively nondeterministic semantics for expressions, in which actions can be executed in nearly any order, and a store semantics that generalizes Sarkar et al.'s and Alglave et al.'s models of the Power architecture. We establish several results for RMC, including sequential consistency for two programming disciplines, and an appropriate notion of type safety. All our results are formalized in Coq.

Skip Supplemental Material Section

Supplemental Material

p623-sidebyside.mpg

References

  1. S. Adve and K. Gharachorloo. Shared memory consistency models: A tutorial. IEEE Computer, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. J. Alglave. A Shared Memory Poetics. PhD thesis, Université Paris VII, Nov. 2010.Google ScholarGoogle Scholar
  3. J. Alglave. A formal hierarchy of weak memory models. Formal Methods in System Design, 41: 178--210, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. J. Alglave, L. Maranget, S. Sarkar, and P. Sewell. Fences in weak memory models. In Twenty-Second International Conference on Computer Aided Verification, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. J. Alglave, L. Maranget, and M. Tautschnig. Herding cats: Modelling, simulation, testing, and data-mining for weak memory. ACM Transactions on Programming Languages and Systems, 2014. To appear. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. M. Batty and P. Sewell. The thin-air problem. Working note, available at http://www.cl.cam.ac.uk/ pes20/cpp/notes42.html, Feb. 2014.Google ScholarGoogle Scholar
  7. M. Batty, S. Owens, S. Sarkar, P. Sewell, and T. Weber. Mathematizing CGoogle ScholarGoogle Scholar
  8. concurrency: The post-Rapperswil model. Technical Report N3132, ISO IEC JTC1/SC22/WG21, Aug. 2010. Available electronically at www.open-std.org/jtc1/sc22/wg21/docs/papers/2010/n3132.pdf.Google ScholarGoogle Scholar
  9. M. Batty, S. Owens, S. Sarkar, P. Sewell, and T. Weber. Mathematizing CGoogle ScholarGoogle Scholar
  10. concurrency. In Thirty-Eighth ACM Symposium on Principles of Programming Languages, Austin, Texas, Jan. 2011.Google ScholarGoogle Scholar
  11. M. Batty, K. Memarian, S. Owens, S. Sarkar, and P. Sewell. Clarifying and compiling C/CGoogle ScholarGoogle Scholar
  12. concurrency: from CGoogle ScholarGoogle Scholar
  13. 11 to POWER. In Thirty-Ninth ACM Symposium on Principles of Programming Languages, Philadelphia, Pennsylvania, Jan. 2012.Google ScholarGoogle Scholar
  14. M. Batty, M. Dodds, and A. Gotsman. Library abstraction for C/CGoogle ScholarGoogle Scholar
  15. concurrency. In Fortieth ACM Symposium on Principles of Programming Languages, Rome, Italy, Jan. 2013.Google ScholarGoogle Scholar
  16. H.-J. Boehm and S. V. Adve. Foundations of the CGoogle ScholarGoogle Scholar
  17. concurrency memory model. In 2008 SIGPLAN Conference on Programming Language Design and Implementation, Tucson, Arizona, June 2008.Google ScholarGoogle Scholar
  18. K. Crary and M. J. Sullivan. A calculus for relaxed memory. Technical Report Carnegie Mellon University-CS-14--139, Carnegie Mellon University, School of Computer Science, 2014.Google ScholarGoogle Scholar
  19. R. Grisenthwaite. ARM barrier litmus tests and cookbook. http://infocenter.arm.com/help/topic/com.arm.doc.genc007826/Barrier_Litmus_Tests_and_Cookbook_A08.pdf, 2009.Google ScholarGoogle Scholar
  20. D. Howells and P. E. McKenney. Circular buffers. https://www.kernel.org/doc/Documentation/circular-buffers.txt.Google ScholarGoogle Scholar
  21. IBM. Power ISA™ version 2.06 revision B, 2010.Google ScholarGoogle Scholar
  22. R. Jagadeesan, C. Pitcher, and J. Riely. Generative operational semantics for relaxed memory models. In Nineteenth European Symposium on Programming, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. L. Lamport. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Transactions on Computers, C-28 (9), Sept. 1979. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. J. Manson, W. Pugh, and S. V. Adve. The Java memory model. In Thirty-Second ACM Symposium on Principles of Programming Languages, Long Beach, California, Jan. 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. J. Polakow. Ordered Linear Logic and Applications. PhD thesis, Carnegie Mellon University, School of Computer Science, Pittsburgh, Pennsylvania, Aug. 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. J. C. Reynolds. Types, abstraction and parametric polymorphism. In Information Processing '83, pages 513--523. North-Holland, 1983. Proceedings of the IFIP 9th World Computer Congress.Google ScholarGoogle Scholar
  27. Sarkar, Sewell, Alglave, and Maranget}sarkarGoogle ScholarGoogle Scholar
  28. :leapfrog-codeS. Sarkar, P. Sewell, J. Alglave, and L. Maranget. ppcmem executable model (ARM version). Unpublished code, 2011\natexlaba.Google ScholarGoogle Scholar
  29. Sarkar, Sewell, Alglave, Maranget, and Williams}sarkarGoogle ScholarGoogle Scholar
  30. :powerS. Sarkar, P. Sewell, J. Alglave, L. Maranget, and D. Williams. Understanding POWER multiprocessors. In 2011 SIGPLAN Conference on Programming Language Design and Implementation, San Jose, California, June 2011\natexlabb. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. P. Sewell, S. Sarkar, S. Owens, F. Z. Nardelli, and M. O. Myreen. x86-TSO: A rigorous and usable programmer's model for x86 multiprocessors. Communications of the ACM, 53 (7), July 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. A. K. Wright and M. Felleisen. A syntactic approach to type soundness. Information and Computation, 115: 38--94, 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. A Calculus for Relaxed Memory

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in

    Full Access

    • Published in

      cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 50, Issue 1
      POPL '15
      January 2015
      682 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/2775051
      • Editor:
      • Andy Gill
      Issue’s Table of Contents
      • cover image ACM Conferences
        POPL '15: Proceedings of the 42nd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages
        January 2015
        716 pages
        ISBN:9781450333009
        DOI:10.1145/2676726

      Copyright © 2015 ACM

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 14 January 2015

      Check for updates

      Qualifiers

      • research-article

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader
    About Cookies On This Site

    We use cookies to ensure that we give you the best experience on our website.

    Learn more

    Got it!