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Optimizing Transfers of Control in the Static Pipeline Architecture

Published:04 June 2015Publication History
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Abstract

Statically pipelined processors offer a new way to improve the performance beyond that of a traditional in-order pipeline while simultaneously reducing energy usage by enabling the compiler to control more fine-grained details of the program execution. This paper describes how a compiler can exploit the features of the static pipeline architecture to apply optimizations on transfers of control that are not possible on a conventional architecture. The optimizations presented in this paper include hoisting the target address calculations for branches, jumps, and calls out of loops, performing branch chaining between calls and jumps, hoisting the setting of return addresses out of loops, and exploiting conditional calls and returns. The benefits of performing these transfer of control optimizations include a 6.8% reduction in execution time and a 3.6% decrease in estimated energy usage.

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    • Published in

      cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 50, Issue 5
      LCTES '15
      May 2015
      141 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/2808704
      • Editor:
      • Andy Gill
      Issue’s Table of Contents
      • cover image ACM Conferences
        LCTES'15: Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM
        June 2015
        149 pages
        ISBN:9781450332576
        DOI:10.1145/2670529

      Copyright © 2015 ACM

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 4 June 2015

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