skip to main content
research-article

Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors

Authors Info & Claims
Published:08 December 2015Publication History
Skip Abstract Section

Abstract

Multiprocessors have become the main architecture trend in modern systems due to the superior performance; nevertheless, the power consumption remains a critical challenge. Global power management (GPM) aims at dynamically finding the power state combination that satisfies the power budget constraint while maximizing the overall performance (or vice versa). Due to the increasing number of cores in a multiprocessor system, the scalability of GPM policies has become critical when searching satisfactory state combinations within acceptable time. This article proposes a highly scalable policy based on combinatorial optimization with theoretical proofs, whereas previous works take exhaustive search or heuristic methods. The proposed policy first applies an optimum algorithm to construct a state combination table in pseudo--polynomial time using dynamic programming. Then, the state combination is assigned to cores with minimum transition cost in linear time by mapping to the network flow problem. Simulation results show that the proposed policy achieves better system performance for any given power budget when compared to the state-of-the-art heuristic. Furthermore, the proposed policy demonstrates its prominent scalability with 125 times faster policy runtime for 512 cores.

References

  1. ACPI. 2011. ACPI—Advanced Configuration and Power Interface Specification. Available at http://www.acpi.info/Google ScholarGoogle Scholar
  2. AMD. 2013. AMD PowerNow! Technology. Available at http://www.amd.com/us/products/technologies/amd-powernow-technology/Pages/amd-powernow-technology.aspxGoogle ScholarGoogle Scholar
  3. ARM. 2005. ARM Intelligent Energy Controller Technical Overview. http://www.arm.com/Google ScholarGoogle Scholar
  4. ARM. 2008. Cortex-A9 MPCore Technical Reference Manual. ARM.Google ScholarGoogle Scholar
  5. Intel. 2013. Enhanced Intel SpeedStep Technology. Retrieved August 13, 2015, from http://www3.intel.com/cd/channel/reseller/asmo-na/eng/203838.htmGoogle ScholarGoogle Scholar
  6. Luca Benini, Alessandro Bogliolo, and Giovanni De Micheli. 2000. A survey of design techniques for system-level dynamic power management. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8, 3, 299--316. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Khurram Bhatti, Cecile Belleudy, and Michel Auguin. 2010. Power management in real time embedded systems through online and adaptive interplay of DPM and DVFS policies. In Proceedings of the IEEE/IFIP International Conference on Embedded and Ubiquitous Computing. 184--191. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Juan M. Cebrian, Juan L. Aragon, and Stefanos Kaxiras. 2011. Power token balancing: Adapting CMPs to power constraints for parallel multithreaded workloads. In Proceedings of the IEEE International Parallel and Distributed Processing Symposium. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Ryan Cochran and Sherief Reda. 2012. Thermal prediction and adaptive control through workload phase detection. ACM Transactions on Design Automation of Electronic Systems 18, 1, Article No. 7. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Jack Edmonds and Richard M. Karp. 1972. Theoretical improvements in algorithmic efficiency for network flow problems. Journal of the Association for Computing Machinery 19, 2, 248--264. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Yang Ge, Parth Malani, and Qinru Qiu. 2010. Distributed task migration for thermal management in many-core systems. In Proceedings of the 47th ACM/IEEE Design Automation Conference. 579--584. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Vinay Hanumaiah, Sarma Vrudhula, and Karam S. Chatha. 2011. Performance optimal online DVFS and task migration techniques for thermally constrained multi-core processors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, 11, 1677--1690. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Jim Held, Jerry Bautista, and Sean Koehi. 2006. From a Few Cores to Many: A Tera-Scale Computing Research Overview. Technical Report. Intel Corporation.Google ScholarGoogle Scholar
  14. John L. Henning. 2006. SPEC CPU2006 benchmark descriptions. SIGARCH Computer Architecture News 34, 4, 1--17. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Sebastian Herbert and Diana Marculescu. 2007. Analysis of dynamic voltage/frequency scaling in chip-multiprocessors. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design. 38--43. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Sebastian Herbert and Diana Marculescu. 2009. Variation-aware dynamic voltage/frequency scaling. In Proceedings of the International Symposium on High Performance Computer Architecture. 1--12.Google ScholarGoogle ScholarCross RefCross Ref
  17. Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, and Margaret Martonosi. 2006. An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture. 347--358. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Niraj K. Jha. 2001. Low power system scheduling and synthesis. In Proceedings of the 2001 IEEE/ACM International Conference on Computer Aided Design. 259--263. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Martonosi, and Douglas W. Clark. 2005. Coordinated, distributed, formal energy management of chip multiprocessors. In Proceedings of the 2005 International Symposium on Low Power Electronics and Design. 127--130. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Wonyoung Kim, Meeta S. Gupta, Gu-Yeon Wei, and David Brooks. 2008. System level analysis of fast, per-core DVFS using on-chip switching regulators. In Proceedings of the IEEE 14th International Symposium on High Performance Computer Architecture. 123--134.Google ScholarGoogle Scholar
  21. Matthias Knoth. 2009. Power management in an embedded multiprocessor cluster. In Proceedings of the Embedded World Conference.Google ScholarGoogle Scholar
  22. Harold W. Kuhn. 2010. The Hungarian method for the assignment problem. In 50 Years of Integer Programming 1958--2008, J. Junger, Th. M. Liebling, D. Naddef, G. L. Nemhauser, W. R. Pullyblank, G. Reinelt, G. Rinaldi, and L. A. Wolsey (Eds.). Springer, 29--47.Google ScholarGoogle Scholar
  23. Jungseob Lee and Nam Sung Kim. 2009. Optimizing total power of many-core processors considering voltage scaling limit and process variations. In Proceedings of the 14th ACM/IEEE International Symposium on Low Power Electronics and Design. 201--206. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Jian Li and Jose F. Martinez. 2005. Power-performance considerations of parallel computing on chip multiprocessors. ACM Transactions on Architecture and Code Optimization 2, 4, 397--422. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, and Norman P. Jouppi. 2009. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture. 469--480. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Kai Ma, Xue Li, Ming Chen, and Xiaorui Wang. 2011a. Scalable power control for many-core architectures running multi-threaded applications. ACM SIGARCH Computer Architecture News 39, 3, 449--460. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. Kai Ma, Xiaorui Wang, and Yefu Wang. 2011b. DPPC: Dynamic power partitioning and capping in chip multiprocessors. In Proceedings of the 2011 IEEE 29th International Conference on Computer Design. 39--44. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Martina Maggio, Henry Hoffmann, Alessandro V. Papadopoulos, Jacopo Panerati, Marco D. Santambrogio, Anant Agarwal, and Alberto Leva. 2012. Comparison of decision-making strategies for self-optimization in autonomic computing systems. ACM Transactions on Autonomous and Adaptive Systems 7, 4, 36:1--36:32. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Grigorios Magklis, Pedro Chaparro, Jose Gonzalez, and Antonio Gonzalez. 2006. Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture. In Proceedings of the 2006 International Symposium on Low Power Electronics and Design. 49--54. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Ke Meng, Russ Joseph, Robert P. Dick, and Li Shang. 2008. Multi-optimization power management for chip multiprocessors. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques. 177--186. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. Asit K. Mishra, Shekhar Srikantaiah, Mahmut Kandemir, and Chita R. Das. 2010. CPM in CMPs: Coordinated power management in chip-multiprocessors. In Proceedings of the 2010 International Conference for High Performance Computing, Networking, Storage, and Analysis. 1--12. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. Massoud Pedram. 1996. Power minimization in IC design: Principles and applications. ACM Transactions on Design Automation of Electronic Systems 1, 1, 3--56. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. Karthick Rajamani, Heather Hanson, Juan Rubio, Soraya Ghiasi, and Freeman Rawson. 2006. Application-aware power management. In Proceedings of the 2006 IEEE International Symposium on Workload Characterization. 39--48.Google ScholarGoogle ScholarCross RefCross Ref
  34. Krishna K. Rangan, Gu-Yeon Wei, and David Brooks. 2009. Thread motion: Fine-grained power management for multi-core systems. In Proceedings of the 36th Annual International Symposium on Computer Architecture. 302--313. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. John Sartori and Rakesh Kumar. 2009. Distributed peak power management for many-core architectures. In Proceedings of the Conference on Design, Automation, and Test in Europe. 1--4. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. Joseph Sharkey, Alper Buyuktosunoglu, and Pradip Bose. 2007. Evaluating design tradeoffs in on-chip power management for CMPs. In Proceedings of the 2007 International Symposium on Low Power Electronics and Design. 44--49. Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. Hao Shen, Ying Tan, Jun Lu, Qing Wu, and Qinru Qiu. 2013. Achieving autonomous power management using reinforcement learning. ACM Transactions on Design Automation of Electronic Systems 18, 2, Article No. 24. Google ScholarGoogle ScholarDigital LibraryDigital Library
  38. Meeta Srivastav, Michael B. Henry, and Leyla Nazhandali. 2012. Design of energy-efficient, adaptable throughput systems at near/sub-threshold voltage. ACM Transactions on Design Automation of Electronic Systems 18, 1, Article No. 3. Google ScholarGoogle ScholarDigital LibraryDigital Library
  39. Emil Talpes and Diana Marculescu. 2005. Toward a multiple clock/voltage island design style for power-aware processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, 5, 591--603. Google ScholarGoogle ScholarDigital LibraryDigital Library
  40. Radu Teodorescu and Josep Torrellas. 2008. Variation-aware application scheduling and power management for chip multiprocessors. In Proceedings of the 35th Annual International Symposium on Computer Architecture. 363--374. Google ScholarGoogle ScholarDigital LibraryDigital Library
  41. Rafael Ubal, Julio Sahuquillo, Salvadore Petit, and Pedro López. 2007. Multi2Sim: A simulation framework to evaluate multicore-multithreaded processors. In Proceedings of the 19th International Symposium on Computer Architecture and High Performance Computing. 62--68.Google ScholarGoogle ScholarCross RefCross Ref
  42. Xiaorui Wang, Kai Ma, and Yefu Wang. 2011. Adaptive power control with online model estimation for chip multiprocessors. IEEE Transactions on Parallel and Distributed Systems 22, 10, 1681--1696. Google ScholarGoogle ScholarDigital LibraryDigital Library
  43. Jonathan A. Winter, David H. Albonesi, and Christine A. Shoemaker. 2010. Scalable thread scheduling and global power management for heterogeneous many-core architectures. In Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques. 29--40. Google ScholarGoogle ScholarDigital LibraryDigital Library
  44. Frances Yao, Alan Demers, and Scott Shenker. 1995. A scheduling model for reduced CPU energy. In Proceedings of the 36th Annual Symposium on Foundations of Computer Science. 374--382. Google ScholarGoogle ScholarDigital LibraryDigital Library
  45. Francesco Zanini, David Atienza, Colin N. Jones, Luca Benini, and Giovanni De Micheli. 2012. Online thermal control methods for multiprocessor systems. ACM Transactions on Design Automation of Electronic Systems 18, 1, Article No. 6. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors

          Recommendations

          Comments

          Login options

          Check if you have access through your login credentials or your institution to get full access on this article.

          Sign in

          Full Access

          PDF Format

          View or Download as a PDF file.

          PDF

          eReader

          View online with eReader.

          eReader
          About Cookies On This Site

          We use cookies to ensure that we give you the best experience on our website.

          Learn more

          Got it!