Abstract
Self-timed chip designs are commonly specified in a high-level message-passing language called CHP. This language is closely related to Hoare's CSP except it admits erroneous behavior due to the necessary limitations of efficient hardware implementations. For example, two processes sending on the same channel at the same time causes glitches and short circuits in the physical chip implementation. If a CHP program maintains certain invariants, such as only one process is sending on any given channel at a time, it can guarantee an error-free execution that behaves much like a CSP program would. In this paper, we present an inferable effect system for ensuring that these invariants hold, drawing from model-checking methodologies while exploiting language-usage patterns and domain-specific specializations to achieve efficiency. This analysis is sound, and is even complete for the common subset of CHP programs without data-sensitive synchronization. We have implemented the analysis and demonstrated that it scales to validate even microprocessors.
- J. V. Arthur, P. A. Merolla, F. Akopyan, R. Alvarez, A. Cassidy, S. Chandra, S. K. Esser, N. Imam, W. Risk, D. B. D. Rubin, et al. Building block of a programmable neuromorphic substrate: A digital neurosynaptic core. In International Joint Conference on Neural Networks, 2012.Google Scholar
- D. Borrione, M. Boubekeur, E. Dumitrescu, M. Renaudin, J.-B. Rigaud, and A. Sirianni. An approach to the introduction of formal validation in an asynchronous circuit design flow. In Hawaii International Conference on System Sciences, 2003. Google Scholar
Digital Library
- A. Cerone and G. J. Milne. A methodology for the formal analysis of asynchronous micropipelines. In Formal Methods in Computer-Aided Design, 2000. Google Scholar
Digital Library
- E. M. Clarke, D. E. Long, and K. L. McMillan. Compositional model checking. In LICS, 1989. Google Scholar
Digital Library
- E. M. Clarke, O. Grumberg, and D. Peled. Model Checking. MIT press, 1999. Google Scholar
Digital Library
- E. W. Dijkstra. Guarded commands, nondeterminacy and formal derivation of programs. Communications of the ACM, 18(8):453–457, 1975. Google Scholar
Digital Library
- J. C. Ebergen. Translating Programs into Delay-Insensitive Circuits. Centrum voor Wiskunde en Informatica, 1989. Google Scholar
Digital Library
- D. Fang, J. Teifel, and R. Manohar. A high-performance asynchronous FPGA: Test results. In Symposium on Field-Programmable Custom Computing Machines, 2005. Google Scholar
Digital Library
- P. Godefroid, J. van Leeuwen, J. Hartmanis, G. Goos, and P. Wolper. Partial-Order Methods for the Verification of Concurrent Systems: An Approach to the State-Explosion Problem. Springer-Verlag, 1996. Google Scholar
Digital Library
- R. Ho, K. W. Mai, and M. A. Horowitz. The future of wires. Proceedings of the IEEE, 89(4):490–504, 2001.Google Scholar
Cross Ref
- C. A. R. Hoare. Communicating sequential processes. Communications of the ACM, 21:666–677, 1978. Google Scholar
Digital Library
- G. J. Holzmann. The SPIN Model Checker: Primer and Reference Manual. Addison-Wesley Professional, 2004. Google Scholar
Digital Library
- ITRS. International Technology Roadmap for Semiconductors: 2012 update, 2012. URL http://www.itrs.net/.Google Scholar
- M. Kishinevsky, A. Kondratyev, A. Taubin, V. Varshavsky, A. Yakovlev, E. Napelbaum, and O. Reva. Concurrent Hardware: The Theory and Practice of Self-Timed Design. John Wiley & Sons, Inc., 1994. Google Scholar
Digital Library
- A. Lines. Pipelined asynchronous circuits. Master’s thesis, California Institute of Technology, 1998.Google Scholar
Digital Library
- S. Longfield, B. Nkounkou, R. Manohar, and R. Tate. Preventing glitches and short circuits in high-level self-timed chip specifications artifact. Cornell University, 2015.Google Scholar
- R. Manohar and A. J. Martin. Quasi-delay-insensitive circuits are Turing-complete. In International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1996.Google Scholar
- A. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, and T. K. Lee. The design of an asynchronous MIPS R3000 microprocessor. In Advanced Research in VLSI, 1997. Google Scholar
Digital Library
- A. J. Martin. The probe: An addition to communication primitives. Information Processing Letters, 20(3):125–130, 1985.Google Scholar
Cross Ref
- A. J. Martin. Distributed mutual exclusion on a ring of processes. Science of Computer Programming, 5:265–276, 1985. Google Scholar
Digital Library
- A. J. Martin. Compiling communicating processes into delayinsensitive VLSI circuits. Distributed Computing, 1(4):226–234, 1986.Google Scholar
Cross Ref
- A. J. Martin. The design of an asynchronous microprocessor. Technical report, California Institute of Technology, 1989. Google Scholar
Digital Library
- A. J. Martin. The limitations to delay-insensitivity in asynchronous circuits. In MIT Conference on Advanced Research in VLSI, 1990. Google Scholar
Digital Library
- The Coq development team. The Coq proof assistant reference manual. LogiCal Project, 2012. Version 8.4.Google Scholar
- M. Mendler and T. Stroup. Newtonian arbiters cannot be proven correct. Formal Methods in System Design, 3(3):233–257, 1993. Google Scholar
Digital Library
- B. Mishra and E. Clarke. Hierarchical verification of asynchronous circuits using temporal logic. Theoretical Computer Science, 38:269– 291, 1985.Google Scholar
- D. E. Muller and W. S. Bartky. A Theory of Asynchronous Circuits. University of Illinois, Graduate College, Digital Computer Laboratory, 1957.Google Scholar
- T. Murata. Petri nets: Properties, analysis and applications. Proceedings of the IEEE, 77(4):541–580, 1989.Google Scholar
Cross Ref
- K. Papadantonakis. Rigorous Analog Verification of Asynchronous Circuits. PhD thesis, California Institute of Technology, 2005. Google Scholar
Digital Library
- A. W. Roscoe, P. H. B. Gardiner, M. H. Goldsmith, J. R. Hulance, D. M. Jackson, and J. B. Scattergood. Hierarchical compression for model-checking CSP or how to check 1020 dining philosophers for deadlock. In Tools and Algorithms for the Construction and Analysis of Systems, 1995. Google Scholar
Digital Library
- B. R. Sheikh and R. Manohar. An operand-optimized asynchronous IEEE 754 double-precision floating-point adder. In ASYNC, 2010. Google Scholar
Digital Library
- S. F. Smith and A. E. Zwarico. Provably correct synthesis of asynchronous circuits. Designing Correct Circuits, 5:237–260, 1992. Google Scholar
Digital Library
- S. F. Smith and A. E. Zwarico. Correct compilation of specifications to deterministic asynchronous circuits. In Formal Methods in System Design, 1995. Google Scholar
Digital Library
- B. Tang, S. Longfield, S. Bhave, and R. Manohar. A low power asynchronous GPS baseband processor. In ASYNC, 2012. Google Scholar
Digital Library
- R. Tate. The sequential semantics of producer effect systems. In POPL, 2013. Google Scholar
Digital Library
- V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, and F. Baez. Reducing power in high-performance microprocessors. In Design Automation Conference, 1998. Google Scholar
Digital Library
- M. van der Goot. Semantics of VLSI Synthesis. PhD thesis, California Institute of Technology, 1995. Google Scholar
Digital Library
- T. Verhoeff. Delay-insensitive codes – an overview. Distributed Computing, 3(1):1–8, 1988.Google Scholar
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Preventing glitches and short circuits in high-level self-timed chip specifications
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