Abstract
Advanced solid-state disks (SSDs) have been equipped with page-mapping flash translation layers and multichannel architectures. The SSDs employ a RAM-based write buffer, which delays write requests for reducing write traffic, reorders requests for mitigating garbage-collection overhead, and produces parallel page writes for improving channel time utilization. This work presents a novel write buffer algorithm that exploits temporal and spatial correlations among buffer pages. The write-buffer groups temporally or spatially correlate buffer pages and then write the grouped buffer pages to the same flash block. In this way, when the correlated page data are updated in the future, flash blocks will receive bulk page invalidations and become good candidates for garbage collection. With multichannel architectures, the write buffer adaptively disperses read-most sequential data over channels for high page-level parallelism of sequential reads, while clustering write-most sequential data in the same channel for a reduced cost of garbage collection. We evaluated the proposed method and previously proposed buffer algorithms. Our method was shown to outperform the existing methods by up to 134%. We also implemented our buffer design on the OpenSSD platform; the time and space overheads of our design were reported to be very low.
- Nitin Agrawal, Vijayan Prabhakaran, Ted Wobber, John D. Davis, Mark Manasse, and Rina Panigrahy. 2008. Design tradeoffs for SSD performance. In Proceedings of the USENIX 2008 Annual Technical Conference on Annual Technical Conference (ATC'08). USENIX Association, 57--70. Google Scholar
Digital Library
- Da-Wei Chang, Hsin-Hung Chen, Dau-Jieu Yang, and Hsung-Pin Chang. 2014. BLAS: Block-level adaptive striping for solid-state drives. ACM Transactions on Design Automation of Electronic Systems 19, 2, 21. Google Scholar
Digital Library
- Li-Pin Chang. 2010. A hybrid approach to NAND-flash-based solid-state disks. IEEE Transactions on Computers 59, 10, 1337--1349. Google Scholar
Digital Library
- Li-Pin Chang and You-Chiuan Su. 2011. Plugging versus logging: A new approach to write buffer management for solid-state disks. In Proceedings of the 48th ACM/EDAC/IEEE Design Automation Conference (DAC). 23--28. Google Scholar
Digital Library
- Yuan-Hao Chang, Wei-Lun Lu, Po-Chun Huang, Lue-Jane Lee, and Tei-Wei Kuo. 2010. An efficient FTL design for multi-chipped solid-state drives. In Proceedings of the 2010 IEEE 16th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'10). IEEE, 237--246. Google Scholar
Digital Library
- Feng Chen, Rubao Lee, and Xiaodong Zhang. 2011. Essential roles of exploiting internal parallelism of flash memory based solid state drives in high-speed data processing. In Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA'11). IEEE, 266--277. Google Scholar
Digital Library
- R. Chen, Z. Qin, Y. Wang, D. Liu, Z. Shao, and Y. Guan. 2015. On-demand block-level address mapping in large-scale NAND flash storage systems. IEEE Transactions on Computers 64, 6, 1729--1741.Google Scholar
- Cagdas Dirik and Bruce Jacob. 2009. The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA'09). ACM, New York, NY, 279--289. Google Scholar
Digital Library
- Aayush Gupta, Youngjae Kim, and Bhuvan Urgaonkar. 2009. DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings. In Proceeding of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'09). ACM, New York, NY, 229--240. Google Scholar
Digital Library
- J. Hsieh, H. Lin, and D. Yang. 2013. Multi-channel architecture-based FTL for reliable and high-performance SSD. IEEE Transactions on Computers PP, 99, 1--1. Google Scholar
Digital Library
- Yang Hu, Hong Jiang, Dan Feng, Lei Tian, Hao Luo, and Chao Ren. 2013. Exploring and exploiting the multilevel parallelism inside SSDs for improved performance and endurance. IEEE Transactions on Computers 62, 6, 1141--1155. Google Scholar
Digital Library
- Sheng-Min Huang and Li-Pin Chang. 2014. A locality-preserving write buffer design for page-mapping multichannel SSDs. 2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS). 713--720. Google Scholar
Digital Library
- Indilinx, Inc. 2011. The OpenSSD Project. Retrieved December 21, 2015 from http://www.openssd-project.org/.Google Scholar
- Heeseung Jo, Jeong-Uk Kang, Seon-Yeong Park, Jin-Soo Kim, and Joonwon Lee. 2006. FAB: Flash-aware buffer management policy for portable media players. IEEE Transactions on Consumer Electronics 52, 2, 485--493. Google Scholar
Digital Library
- Sooyong Kang, Sungmin Park, Hoyoung Jung, Hyoki Shim, and Jaehyuk Cha. 2009. Performance trade-offs in using NVRAM write buffer for flash memory-based storage devices. IEEE Transactions on Computers 58, 6, 744--758. Google Scholar
Digital Library
- Dongwook Kim and Sooyong Kang. 2013. Partial page buffering for consumer devices with flash storage. In Proceedings of the Third International Conference on Consumer Electronics. IEEE, 177--180.Google Scholar
Cross Ref
- Hyojun Kim and Seongjun Ahn. 2008. BPLRU: A buffer management scheme for improving random writes in flash storage. In Proceedings of the 6th USENIX Conference on File and Storage Technologies (FAST'08). USENIX Association, Berkeley, CA, 1--14. Google Scholar
Digital Library
- Sungjin Lee, Dongkun Shin, Young-Jin Kim, and Jihong Kim. 2008. LAST: Locality-aware sector translation for NAND flash memory-based storage systems. SIGOPS Operating Systems Review 42, 6, 36--42. Google Scholar
Digital Library
- Sang-Won Lee, Dong-Joo Park, Tae-Sun Chung, Dong-Ho Lee, Sangwon Park, and Ha-Joo Song. 2007. A Log buffer-based flash translation layer using fully-associative sector translation. Transactions on Embedded Computing Systems 6, 3, 18. Google Scholar
Digital Library
- Wen-Huei Lin and Li-Pin Chang. 2012. Dual greedy: Adaptive garbage collection for page-mapping solid-state disks. In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'12). 117--122. Google Scholar
Digital Library
- Duo Liu, Tianzheng Wang, Yi Wang, Zhiwei Qin, and Zili Shao. 2011. PCM-FTL: A write-activity-aware NAND flash memory management scheme for PCM-based embedded systems. In Proceedings of the 2011 IEEE 32nd Real-Time Systems Symposium (RTSS'11). IEEE, 357--366. Google Scholar
Digital Library
- Duo Liu, Yi Wang, Zhiwei Qin, Zili Shao, and Yong Guan. 2012. A space reuse strategy for flash translation layers in SLC NAND flash memory storage systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, 6, 1094--1107. Google Scholar
Digital Library
- Sang-Hoon Park, Seung-Hwan Ha, Kwanhu Bang, and Eui-Young Chung. 2009. Design and analysis of flash translation layers for multi-channel NAND flash-based storage devices. IEEE Transactions on Consumer Electronics 55, 3, 1392--1400. Google Scholar
Digital Library
- Seung-Ho Park, Jung-Wook Park, Shin-Dug Kim, and Charles C Weems. 2012. A pattern adaptive NAND flash memory storage structure. IEEE Transactions on Computers 61, 1, 134--138. Google Scholar
Digital Library
- Sung Kyu Park, Youngwoo Park, Gyudong Shim, and Kyu Ho Park. 2011. CAVE: Channel-aware buffer management scheme for solid state disk. In Proceedings of the 2011 ACM Symposium on Applied Computing (SAC'11). ACM, New York, NY, 346--353. Google Scholar
Digital Library
- Erik Riedel, Catherine van Ingen, and Jim Gray. 1998. Sequential I/O on Windows NT 4.0--achieving top performance. In Proceedings of the 2nd USENIX Windows NT Symposium. 3--5.Google Scholar
- Samsung Electronics Company. 2009. K9GBG08U0A 32Gb A-die MLC NAND Flash Data Sheet. Samsung Electronics Company.Google Scholar
- Dongyoung Seo and Dongkun Shin. 2008. Recently-evicted-first buffer replacement policy for flash storage devices. IEEE Transactions on Consumer Electronics 54, 3, 1228--1235. Google Scholar
Digital Library
- Jinho Seol, Hyotaek Shim, Jaegeuk Kim, and Seungryoul Maeng. 2009. A buffer replacement algorithm exploiting multi-chip parallelism in solid state disks. In Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. ACM, New York, NY, 137--146. Google Scholar
Digital Library
- Yoon Jae Seong, Eyee Hyun Nam, Jin Hyuk Yoon, Hongseok Kim, Jin-Yong Choi, Sookwan Lee, Young Hyun Bae, Jaejin Lee, Yookun Cho, and Sang Lyul Min. 2010. Hydra: A block-mapped parallel flash memory solid-state disk architecture. IEEE Transactions on Computers 59, 905--921. Google Scholar
Digital Library
- Liang Shi, Jianhua Li, C. J. Xue, Chengmo Yang, and Xuehai Zhou. 2011. ExLRU: A unified write buffer cache management for flash memory. In Proceedings of the International Conference on Embedded Software (EMSOFT'11). 339--348. Google Scholar
Digital Library
- Gyudong Shim, Youngwoo Park, and Kyu Ho Park. 2011. A hybrid flash translation layer with adaptive merge for SSDs. ACM Transactions on Storage 6, 4, Article 15, 27 pages. Google Scholar
Digital Library
- Tianzheng Wang, Duo Liu, Yi Wang, and Zili Shao. 2013. FTL 2: A hybrid flash translation layer with logging for write reduction in flash memory. In ACM SIGPLAN Notices, Vol. 48. ACM, New York, NY, 91--100. Google Scholar
Digital Library
- Qingsong Wei, Cheng Chen, and Jun Yang. 2014. CBM: A cooperative buffer management for SSD. In Proceedings of the 2014 30th Symposium on Mass Storage Systems and Technologies (MSST'14). 1--12.Google Scholar
Cross Ref
Index Terms
Exploiting Page Correlations for Write Buffering in Page-Mapping Multichannel SSDs
Recommendations
A Locality-Preserving Write Buffer Design for Page-Mapping Multichannel SSDs
HPCC '14: Proceedings of the 2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS)Advanced SSDs employ a RAM-based write buffer to improve their write performance. The buffer intentionally delays write requests in order to reduce flash write traffic and reorders them to minimize the cost of garbage collection. This work presents a ...
Plugging Versus Logging: Adaptive Buffer Management for Hybrid-Mapping SSDs
A promising technique to improve the write performance of solid-state disks (SSDs) is to use a disk write buffer. The goals of a write buffer is not only to reduce the write traffic to the flash chips but also to convert host write patterns into long ...
An adaptive, low-cost wear-leveling algorithm for multichannel solid-state disks
Multilevel flash memory cells double or even triple storage density, producing affordable solid-state disks for end users. As flash memory endures only limited program-erase cycles, solid-state disks employ wear-leveling methods to prevent any portions ...






Comments