skip to main content
research-article

Separation Logic for High-Level Synthesis

Published:17 December 2015Publication History
Skip Abstract Section

Abstract

High-Level Synthesis (HLS) promises a significant shortening of the FPGA design cycle by raising the abstraction level of the design entry to high-level languages such as C/C++. However, applications using dynamic, pointer-based data structures and dynamic memory allocation remain difficult to implement well, yet such constructs are widely used in software. Automated optimizations that leverage the memory bandwidth of FPGAs by distributing the application data over separate banks of on-chip memory are often ineffective in the presence of dynamic data structures due to the lack of an automated analysis of pointer-based memory accesses. In this work, we take a step toward closing this gap. We present a static analysis for pointer-manipulating programs that automatically splits heap-allocated data structures into disjoint, independent regions. The analysis leverages recent advances in separation logic, a theoretical framework for reasoning about heap-allocated data that has been successfully applied in recent software verification tools. Our algorithm focuses on dynamic data structures accessed in loops and is accompanied by automated source-to-source transformations that enable automatic loop parallelization and memory partitioning by off-the-shelf HLS tools. We demonstrate the successful loop parallelization and memory partitioning by our tool flow using three real-life applications that build, traverse, update, and dispose of dynamically allocated data structures. Our case studies, comparing the automatically parallelized to the direct HLS implementations, show an average latency reduction by a factor of 2 × across our benchmarks.

References

  1. Jonathan Babb, Martin Rinard, Andras Moritz, Walter Lee, Matthew Frank, Rajeev Barua, and Saman Amarasinghe. 1999. Parallelizing applications into silicon. In Proceedings of the Symposium on Field-Programmable Custom Computing Machines. IEEE, Napa Valley, CA, 70--80. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. BDTI. 2010. An Independent Evaluation of: The AutoESL AutoPilot High-Level Synthesis Tool. Retrieved March 2, 2014 from http://www.bdti.com/Resources/BenchmarkResults/HLSTCP/AutoPilot.Google ScholarGoogle Scholar
  3. Mohamed-Walid Benabderrahmane, Louis-Noel Pouchet, Albert Cohen, and Cédric Bastoul. 2010. The polyhedral model is more widely applicable than you think. In Proceedings of the International Conference on Compiler Construction. Springer-Verlag, Paphos, Cyprus, 283--303. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Josh Berdine, Cristiano Calcagno, and Peter O’Hearn. 2005. Symbolic execution with separation logic. In Proceedings of the Asian Conference on Programming Languages and Systems. Tsukuba, Japan, 52--68. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Uday Bondhugula, Albert Hartono, J. Ramanujam, and P. Sadayappan. 2008. A practical automatic polyhedral parallelizer and locality optimizer. SIGPLAN Notices 43, 6 (June 2008), 101--113. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Matko Botinčan, Dino Distefano, Mike Dodds, Radu Grigore, and Matthew J. Parkinson. 2011. coreStar: The core of jStar. Boogie (2011), 65--77.Google ScholarGoogle Scholar
  7. Matko Botinčan, Mike Dodds, and Suresh Jagannathan. 2013. Proof-directed parallelization synthesis by separation logic. ACM Transactions on Programming Languages and Systems 35, 2 (July 2013), 1--60. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Cristiano Calcagno and Dino Distefano. 2011. Infer: An automatic program verifier for memory safety of C programs. In Proceedings of the International Conference on NASA Formal Methods. Springer-Verlag, Pasadena, CA, 459--465. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason H. Anderson, Stephen Brown, and Tomasz Czajkowski. 2011. LegUp: High-level synthesis for FPGA-based processor/accelerator systems. In Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays. ACM, Monterey, CA, 33--36. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Jason Cong, Wei Jiang, Bin Liu, and Yi Zou. 2011. Automatic memory partitioning and scheduling for throughput and power optimization. ACM Transactions on Design Automation of Electronic Systems 16, 2 (March 2011), 1--25. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Byron Cook, A. Gupta, S. Magill, A. Rybalchenko, J. Simsa, S. Singh, and V. Vafeiadis. 2009. Finding heap-bounds for hardware synthesis. In Proceedings of the Conference on Formal Methods in Computer-Aided Design. IEEE, Austin, TX, 205--212.Google ScholarGoogle Scholar
  12. Byron Cook, Stephen Magill, Mohammad Raza, Jiri Simsa, and Satnam Singh. 2010. Making Fast Hardware with Separation Logic. Retrieved from http://www.cs.cmu.edu/∼smagill/papers/fast-hardware.pdf.Google ScholarGoogle Scholar
  13. Paul Feautrier. 1991. Dataflow analysis of array and scalar references. International Journal of Parallel Programming 20, 1 (1991), 23--53.Google ScholarGoogle ScholarCross RefCross Ref
  14. Rakesh Ghiya, L Hendren, and Yingchun Zhu. 1998. Detecting parallelism in C programs with recursive data structures. IEEE Transactions on Parallel and Distributed Systems 1 (1998), 35--47. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Bolei Guo, Neil Vachharajani, and David I. August. 2007. Shape analysis with inductive recursion synthesis. ACM SIGPLAN Notices 42, 6 (June 2007), 256. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Qijing Huang, Ruolong Lian, A. Canis, Jongsok Choi, R. Xi, S. Brown, and J. Anderson. 2013. The effect of compiler optimizations on high-level synthesis for FPGAs. In Proceedings of Field-Programmable Custom Computing Machines. IEEE, Seattle, WA, 89--96. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Tapas Kanungo, David M. Mount, Nathan S. Netanyahu, Christine D. Piatko, Ruth Silverman, and Angela Y. Wu. 2002. An efficient k-means clustering algorithm: Analysis and implementation. IEEE Journal of PAMI 24, 7 (July 2002), 881--892. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Chris Lattner and Vikram Adve. 2004. LLVM: A compilation framework for lifelong program analysis transformation. In Proceedings of the International Symposium on Code Generation and Optimization. IEEE Computer Society, Palo Alto, CA, 75--86. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Qiang Liu, George A. Constantinides, Konstantinos Masselos, and Peter Y. K. Cheung. 2007. Automatic on-chip memory minimization for data reuse. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines. IEEE, Napa, CA, 251--260. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. LLNL. 2014. ROSE Compiler Infrastructure. Retrieved from http://rosecompiler.org/.Google ScholarGoogle Scholar
  21. Stephen Magill, A Nanevski, Edmund Clarke, and Peter Lee. 2006. Inferring invariants in separation logic for imperative list-processing programs. In Proceedings of the Third Workshop on Semantics, Program Analysis, and Computing Environments for Memory Management (SPACE). ACM, Charlotte, SC, 47--60.Google ScholarGoogle Scholar
  22. Wim Meeus, Kristof Van Beeck, Toon Goedemé, Jan Meel, and Dirk Stroobandt. 2012. An overview of todays high-level synthesis tools. Design Automation for Embedded Systems (Aug. 2012), 1--21. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Peter O’Hearn, John Reynolds, and Hongseok Yang. 2001. Local reasoning about programs that alter data structures. In Proceedings of the 15th International Workshop on Computer Science Logic (CSL’01). Springer-Verlag, Paris, France, 1--19. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Louis-Noel Pouchet, Peng Zhang, P. Sadayappan, and Jason Cong. 2013. Polyhedral-based data reuse optimization for configurable computing. In Proceedings of the International Symposium on Field Programmable Gate Arrays. ACM, Monterey, CA, 29--38. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Mohammad Raza, Cristiano Calcagno, and Philippa Gardner. 2009. Automatic parallelization with separation logic. In Proceedings of the International Symposium on Programming Languages and Systems. Springer-Verlag, York, UK, 348--362. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Luc Séméria, Koichi Sato, and Giovanni De Micheli. 2000. Resolution of dynamic memory allocation and pointers for the behavioral synthesis form C. In Proceedings of the Design, Automation, and Testing in Europe Conference. ACM, Paris, France, 312--319. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. Jason Villarreal, Adrian Park, Walid Najjar, and Robert Halstead. 2010. Designing modular hardware accelerators in C with ROCCC 2.0. In Proceedings of the Symposium on Field-Programmable Custom Computing Machines. IEEE, Charlotte, SC, 127--134. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Robert P. Wilson and Monica S. Lam. 1995. Efficient context-sensitive pointer analysis for C programs. In Proceedings of the Conference on Programming Language Design and Implementation. ACM, La Jolla, CA, 1--12. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Felix Winterstein, Samuel Bayliss, and George A. Constantinides. 2013a. FPGA-based K-means clustering using tree-based data structures. In Proceedings of the International Conference on Field Programmable Logic and Applications. IEEE, Porto, Portugal, 1--6.Google ScholarGoogle Scholar
  30. Felix Winterstein, Samuel Bayliss, and George A. Constantinides. 2013b. High-level synthesis of dynamic data structures: A case study using Vivado HLS. In Proceedings of the International Conference on Field-Programmable Technology. IEEE, Kyoto, Japan, 362--365.Google ScholarGoogle Scholar
  31. Felix Winterstein, Samuel Bayliss, and George A. Constantinides. 2014. Separation logic-assisted code transformations for efficient high-level synthesis. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines. IEEE, Boston, MA, 1--8. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Separation Logic for High-Level Synthesis

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in

    Full Access

    • Published in

      cover image ACM Transactions on Reconfigurable Technology and Systems
      ACM Transactions on Reconfigurable Technology and Systems  Volume 9, Issue 2
      Special Section on RAW2014
      February 2016
      146 pages
      ISSN:1936-7406
      EISSN:1936-7414
      DOI:10.1145/2854101
      • Editor:
      • Steve Wilton
      Issue’s Table of Contents

      Copyright © 2015 ACM

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 17 December 2015
      • Accepted: 1 October 2015
      • Revised: 1 August 2015
      • Received: 1 March 2015
      Published in trets Volume 9, Issue 2

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • research-article
      • Research
      • Refereed

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader
    About Cookies On This Site

    We use cookies to ensure that we give you the best experience on our website.

    Learn more

    Got it!