Abstract
Present-day focus on multicore research has not only increased computing power but also power- and bandwidth-efficient communication among cores. On-chip communication networks have become popular today because of their low energy use and modular structure compared to bus-based interconnects. Silicon photonics has further boosted the performance of on-chip interconnection networks with its low energy-delay product and high reliability. In current multicore Network-on-Chip (NoC) architectures, photonics is playing an important role in transferring large volumes of data both on- and off-chip. The problem addressed in this work is the issue of broadcast traffic arising due to invalidation requests from on-chip cache memories. Although such traffic is typically less than 1% of total traffic, it can easily present a high load on network resources, creating congestion and degrading performance. In this article, we propose a CDMA-based, secure, scalable, and energy-efficient technique to eliminate broadcast invalidations and increase overall performance. Experimental results indicate a performance boost up to 22.2% over a competing Photonic NoC and up to 57.4% over Electrical Mesh-based NoC when the proposed technique is used. Additional hardware deployed has an area overhead of less than 1%, whereas total energy consumed is at par with other state-of-the-art techniques.
- A. Abousamra, R. Melhem, and A. Jones. 2011. Two-hop free-space based optical interconnects for chip multiprocessors. In Proceedings of the 5th IEEE/ACM International Symposium on Networks on Chip 2011 (NoCS'11). 89--96. Google Scholar
Digital Library
- S. Bahirat and S. Pasricha. 2012. A particle swarm optimization approach for synthesizing application-specific hybrid photonic networks-on-chip. In Proceedings of the 13th International Symposium on Quality Electronic Design, 2012 (ISQED'12). 78--83. DOI:http://dx.doi.org/10.1109/ISQED.2012.6187477Google Scholar
- M. Bahmani, M. Reshadi, A. Khademzadeh, and A. Reza. 2008. Corona: Ring-based interconnected topology for on-chip network. In Proceedings of the 3rd International Design and Test Workshop 2008 (IDT'08). 199--204. DOI:http://dx.doi.org/10.1109/IDT.2008.4802497Google Scholar
Cross Ref
- B. Ciftcioglu, Jing Gao, R. Berman, M. Jain, D. Moore, G. Wicks, M. Huang, E. G. Friedman, and Hui Wu. 2012. Recent progress on 3-D integrated intra-chip free-space optical interconnect. In Proceedings of the 2012 IEEE Optical Interconnects Conference (OIC'12). 56--57. DOI:http://dx.doi.org/10.1109/OIC.2012.6224449Google Scholar
Cross Ref
- W. J. Dally and B. Towles. 2001. Route packets, not wires: On-chip interconnection networks. In Proceedings of the Design Automation Conference 2001 (DAC'01). 684--689. DOI:http://dx.doi.org/10.1109/DAC.2001.156225 Google Scholar
Digital Library
- M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen. 2011. Exploring partitioning methods for 3D networks-on-chip utilizing adaptive routing model. In Proceedings of the 5th IEEE/ACM International Symposium on Networks on Chip (NoCS'11). 73--80. Google Scholar
Digital Library
- Paolo Grani and Sandro Bartolini. 2014. Design options for optical ring interconnect in future client devices. Journal of Emerging Technologies and Computer Systems 10, 4, Article 30 (June 2014), 25 pages. DOI:http://dx.doi.org/10.1145/2602155 Google Scholar
Digital Library
- Intel-Labs. 2010. The 50G Silicon Photonics Link. Technical Report. Intel. Retrieved from http://www.intel.com/content/www/us/en/data-center/silicon-photonics-50g-link-paper.html.Google Scholar
- A. Joshi, C. Batten, Yong-Jin Kwon, S. Beamer, I. Shamim, K. Asanovic, and V. Stojanovic. 2009. Silicon-photonic clos networks for global on-chip communication. In Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip 2009 (NoCS 2009). 124--133. DOI:http://dx.doi.org/10.1109/NOCS.2009.5071460 Google Scholar
Digital Library
- Somayyeh Koohi, Yawei Yin, Shaahin Hessabi, and S. J. Ben Yoo. 2014. Towards a scalable, low-power all-optical architecture for networks-on-chip. ACM Transactions on Embedded Computer Systems 13, 3s, Article 101 (March 2014), 30 pages. DOI:http://dx.doi.org/10.1145/2567930 Google Scholar
Digital Library
- S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani. 2002. A network on chip architecture and design methodology. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2002. 105--112. DOI:http://dx.doi.org/10.1109/ ISVLSI.2002.1016885 Google Scholar
Digital Library
- George Kurian, Jason E. Miller, James Psota, Jonathan Eastep, Jifeng Liu, Jurgen Michel, Lionel C. Kimerling, and Anant Agarwal. 2010. ATAC: A 1000-core cache-coherent processor with On-chip optical network. In Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques 2010 (PACT'10). ACM, New York, 477--488. DOI:http://dx.doi.org/10.1145/1854273.1854332 Google Scholar
Digital Library
- Jean-Jacques Lecler and Gilles Baillieu. 2011. Application driven network-on-chip architecture exploration and refinement for a complex SoC. Design Automation for Embedded Systems 15, 2 (2011), 133--158. DOI:http://dx.doi.org/10.1007/s10617-011-9075-5 Google Scholar
Digital Library
- Cheng Li, M. Browning, P. V. Gratz, and S. Palermo. 2014. LumiNOC: A power-efficient, high-performance, photonic network-on-chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, 6 (June 2014), 826--838. DOI:http://dx.doi.org/10.1109/TCAD.2014.2320510Google Scholar
Cross Ref
- C. Li, M. Browning, P. V. Gratz, and S. Palermo. 2012. Energy-efficient optical broadcast for nanophotonic networks-on-chip. In Proceedings of the 2012 IEEE Optical Interconnects Conference (OIC'12). IEEE, 64--65. DOI:http://dx.doi.org/10.1109/OIC.2012.6224445Google Scholar
Cross Ref
- Sheng Li, Jung Ho Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi. 2009. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42), 2009. 469--480. Google Scholar
Digital Library
- Chi-Keung Luk, Robert Cohn, Robert Muth, Harish Patil, Artur Klauser, Geoff Lowney, Steven Wallace, Vijay Janapa Reddi, and Kim Hazelwood. 2005. Pin: Building customized program analysis tools with dynamic instrumentation. SIGPLAN Notes 40, 6 (June 2005), 190--200. DOI:http://dx.doi.org/10.1145/1064978.1065034 Google Scholar
Digital Library
- T. Meincke, A. Hemani, S. Kumar, P. Ellervee, J. Oberg, T. Olsson, P. Nilsson, D. Lindqvist, and H. Tenhunen. 1999. Globally asynchronous locally synchronous architecture for large high-performance ASICs. In Proceedings of the 1999 IEEE International Symposium on Circuits and Systems 1999 (ISCAS'99), Vol. 2. 512--515. DOI:http://dx.doi.org/10.1109/ISCAS.1999.780794Google Scholar
- J. E. Miller, H. Kasture, G. Kurian, C. Gruenwald, N. Beckmann, C. Celio, J. Eastep, and A. Agarwal. 2010. Graphite: A distributed parallel simulator for multicores. In Proceedings of the IEEE 16th International Symposium on High Performance Computer Architecture (HPCA'10). 1--12. DOI:http://dx.doi.org/10.1109/ HPCA.2010.5416635Google Scholar
- M. Mohamed, Zheng Li, Xi Chen, A. Mickelson, and Li Shang. 2011. Modeling and analysis of micro-ring based silicon photonic interconnect for embedded systems. In Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'11). 227--236. Google Scholar
Digital Library
- Benjamin Moss. 2009. High-speed Modulation of Resonant CMOS Photonic Modulators in Deep-submicron Bulk-CMOS. Ph.D. Dissertation. Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science.Google Scholar
- Ian O' Connor and Gabriela Nicolescu (Eds.). 2013. Integrated Optical Interconnect Architectures for Embedded Systems. Springer, New York. DOI:http://dx.doi.org/10.1007/978-1-4419-6193-8 Google Scholar
Digital Library
- Reza Omrani and P. Vijay Kumar. 2006. Codes for Optical CDMA. Lecture Notes in Computer Science, Vol. 4086. Springer, Berlin, Chapter Sequences and Their Applications - SETA, 34--46. DOI:http://dx.doi.org/10.1007/11863854_4 Google Scholar
Digital Library
- J. S. Orcutt and R. J. Ram. 2010. Photonic device layout within the foundry CMOS design environment. IEEE Photonics Technology Letters 22, 8 (April 2010), 544--546. DOI:http://dx.doi.org/10.1109/LPT.2010.2041445Google Scholar
Cross Ref
- Yan Pan, J. Kim, and G. Memik. 2010. FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar. In Proceedings of the IEEE 16th International Symposium on High Performance Computer Architecture (HPCA 2010). 1--12. DOI:http://dx.doi.org/10.1109/ HPCA.2010.5416626Google Scholar
- Yan Pan, Prabhat Kumar, John Kim, Gokhan Memik, Yu Zhang, and Alok Choudhary. 2009. Firefly: Illuminating future network-on-chip with nanophotonics. In Proceedings of the 36th Annual International Symposium on Computer Architecture, 2009 (ISCA'09). ACM, New York, 429--440. DOI:http://dx.doi.org/10.1145/1555754.1555808 Google Scholar
Digital Library
- S. Pasricha and S. Bahirat. 2011. OPAL: A multi-layer hybrid photonic NoC for 3D ICs. In Proceedings of the 16th Asia and South Pacific Design Automation Conference 2011 (ASP-DAC'11). 345--350. DOI:http://dx.doi.org/10.1109/ ASPDAC.2011.5722211 Google Scholar
Digital Library
- Soumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui, and Hafizur Rahaman. 2012a. Design of an NoC with on-chip photonic interconnects using adaptive CDMA links. In Proceedings of the IEEE International SOC Conference (SOCC'12). IEEE, 352--357.Google Scholar
Cross Ref
- Soumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui, and Hafizur Rahaman. 2012b. A photonic network on chip with CDMA links. In Progress in VLSI Design and Test, Hafizur Rahaman, Sanatan Chattopadhyay, and Santanu Chattopadhyay (Eds.). Lecture Notes in Computer Science, Vol. 7373. Springer, Berlin, 377--378. DOI:http://dx.doi.org/10.1007/978-3-642-31494-0_50 Google Scholar
Digital Library
- Soumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui, and Hafizur Rahaman. 2013. An area and power efficient dynamic TDMA based photonic network on chip. In Proceedings of the 2013 International Symposium on Electronic System Design (ISED). IEEE, 113--117. Google Scholar
Digital Library
- Graham T. Reed (Ed.). 2008. Silicon Photonics: The State of the Art (1st. ed.). John Wiley and Sons, West Sussex, England. Google Scholar
Digital Library
- A. Shacham, K. Bergman, and L.P. Carloni. 2008. Photonic networks-on-chip for future generations of chip multiprocessors. IEEE Transactions on Computing 57, 9 (Sept 2008), 1246--1260. DOI:http://dx.doi.org/10.1109/ TC.2008.78 Google Scholar
Digital Library
- A. Shacham, B. G. Lee, A. Biberman, K. Bergman, and L. P. Carloni. 2007. Photonic NoC for DMA communications in chip multiprocessors. In Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects 2007 (HOTI'07). 29--38. DOI:http://dx.doi.org/10.1109/ HOTI.2007.9 Google Scholar
Digital Library
- Daniel J. Sorin, Mark D. Hill, and David A. Wood. 2011. A Primer on Memory Consistency and Cache Coherence. Vol. 6. Morgan and Claypool. 1--212 pages. DOI:http://dx.doi.org/10.2200/S00346ED1V01Y201104CAC016 Google Scholar
Digital Library
- M. B. Stensgaard and J. Sparso. 2008. ReNoC: A network-on-chip architecture with reconfigurable topology. In Proceedings of the 2nd ACM/IEEE International Symposium on Networks-on-Chip 2008 (NoCS'08). 55--64. DOI:http://dx.doi.org/10.1109/ NOCS.2008.4492725 Google Scholar
Digital Library
- Chen Sun, C.-H. O. Chen, G. Kurian, Lan Wei, J. Miller, A. Agarwal, Li-Shiuan Peh, and V. Stojanovic. 2012. DSENT - a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling. In Proceedings of the 6th IEEE/ACM International Symposium on Networks on Chip (NoCS'12). 201--210. DOI:http://dx.doi.org/10.1109/ NOCS.2012.31 Google Scholar
Digital Library
- Xin Wang, T. Ahonen, and J. Nurmi. 2007. Applying CDMA technique to network-on-chip. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15, 10 (Oct 2007), 1091--1100. DOI:http://dx.doi.org/10.1109/TVLSI.2007.903914 Google Scholar
Digital Library
- S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. 1995. The SPLASH-2 programs: Characterization and methodological considerations. In Proceedings of the 22nd Annual International Symposium on Computer Architecture 1995 (ISCA'95). 24--36. Google Scholar
Digital Library
- Qianfan Xu, B. Schmid, J. Shakya, and M. Lipson. 2006. WDM silicon modulators based on micro-ring resonators. In Proceedings of the 19th Annual Meeting of the IEEE Lasers and Electro-Optics Society 2006 (LEOS'06). 647--648. DOI:http://dx.doi.org/10.1109/ LEOS.2006.278862Google Scholar
- Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Weichen Liu, and Mahdi Nikdast. 2012. A torus-based hierarchical optical-electronic network-on-chip for multiprocessor system-on-chip. Journal of Emerging Technologies and Computer Systems 8, 1, Article 5 (Feb. 2012), 26 pages. DOI:http://dx.doi.org/10.1145/2093145.2093150 Google Scholar
Digital Library
- Lei Zhang, Xianfang Tan, Mei Yang, Yingtao Jiang, Peng Liu, and Jianyi Yang. 2012. Circuit-switched on-chip photonic interconnection network. In Proceedings of the IEEE 9th International Conference on Group IV Photonics (GFP'12). 282--284. DOI:http://dx.doi.org/10.1109/GROUP4.2012.6324160Google Scholar
Cross Ref
Index Terms
Design of a High-Performance CDMA-Based Broadcast-Free Photonic Multi-Core Network on Chip
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