Abstract
Real-time systems require a safe and precise estimate of the worst-case execution time (WCET) of programs. In multicore architectures, the precision of a program’s WCET estimate highly depends on the precision of its predicted shared cache behavior. Prediction of shared cache behavior is difficult due to the uncertain timing of interfering shared cache accesses made by programs running on other cores. Given the assignment of programs to cores, the worst-case interference placement (WCIP) technique tries to find the worst-case timing of interfering accesses, which would cause the maximum number of cache misses on the worst case path of the program, to determine its WCET. Although WCIP generates highly precise WCET estimates, the current ILP-based approach is also known to have very high analysis time. In this work, we investigate the WCIP problem in detail and determine its source of hardness. We show that performing WCIP is an NP-hard problem by reducing the 0-1 knapsack problem. We use this observation to make simplifying assumptions, which make the WCIP problem tractable, and we propose an approximate greedy technique for WCIP, whose time complexity is linear in the size of the program. We perform extensive experiments to show that the assumptions do not affect the precision of WCIP but result in significant reduction of analysis time.
- Ernst Althaus, Sebastian Altmeyer, and Rouven Naujoks. 2011. Precise and efficient parametric path analysis. In Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems. Google Scholar
Digital Library
- Sebastian Altmeyer, Claire Maiza, and Jan Reineke. 2010. Resilience analysis: Tightening the CRPD bound for set-associative caches. In Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems. 153--162. Google Scholar
Digital Library
- Sudipta Chattopadhyay, Chong Lee Kee, Abhik Roychoudhury, Timon Kelter, Marwedel Peter, and Falk Heiko. 2012. A unified WCET analysis framework for multi-core platforms. In Proceedings of the Real-Time and Embedded Technology and Applications Symposium. Google Scholar
Digital Library
- Sudipta Chattopadhyay and Abhik Roychoudhury. 2011. Scalable and precise refinement of cache timing analysis via model checking. In Proceedings of the Real-Time Systems Symposium. Google Scholar
Digital Library
- Sudipta Chattopadhyay, Abhik Roychoudhury, and Tulika Mitra. 2010. Modeling shared cache and bus in multi-cores for timing analysis. In Proceedings of the International Workshop on Software and Compilers for Embedded Systems. Google Scholar
Digital Library
- Christian Ferdinand and Reinhard Wilhelm. 1999. Efficient and precise cache behavior prediction for real-time systems. Real-Time Systems 17, 2--3, 131--181. Google Scholar
Digital Library
- Damien Hardy, Thomas Piquet, and Isabelle Puaut. 2009. Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches. In Proceedings of the Real-Time Systems Symposium. Google Scholar
Digital Library
- Damien Hardy and Isabelle Puaut. 2008. WCET analysis of multi-level non-inclusive set-associative instruction caches. In Proceedings of the Real-Time Systems Symposium. Google Scholar
Digital Library
- Timon Kelter, Heiko Falk, Peter Marwedel, Sudipta Chattopadhyay, and Abhik Roychoudhury. 2014. Static analysis of multi-core TDMA resource arbitration delays. Real-Time Systems 50, 2, 185--229. DOI:http://dx.doi.org/10.1007/s11241-013-9189-x Google Scholar
Digital Library
- Benjamin Lesage, Damien Hardy, and Isabelle Puaut. 2010. Shared data cache conflicts reduction for WCET computation in multi-core architectures. In Proceedings of the International Conference on Real-Time Networks and Systems.Google Scholar
- Xianfeng Li, Yun Liang, Tulika Mitra, and Abhik Roychoudury. 2007. Chronos: A timing analyzer for embedded software. Science of Computer Programming 69, 1--3, 56--67. http://www.comp.nus.edu.sg/∼rpembed/chronos. Google Scholar
Digital Library
- Yan Li, Vivy Suhendra, Yun Liang, Tulika Mitra, and Abhik Roychoudhury. 2009. Timing analysis of concurrent programs running on shared cache multi-cores. In Proceedings of the Real-Time Systems Symposium. Google Scholar
Digital Library
- Thomas Lundqvist and Per Stenström. 1999. Timing anomalies in dynamically scheduled microprocessors. In Proceedings of the 20th IEEE Real-Time Systems Symposium (RTSS’99). Google Scholar
Digital Library
- Silvano Martello and Paolo Toth. 1990. Knapsack Problems: Algorithms and Computer Implementations. John Wiley & Sons. Google Scholar
Digital Library
- K. Nagar and Y. N. Srikant. 2015a. Path sensitive cache analysis using cache miss paths. In Verification, Model Checking, and Abstract Interpretation. Springer, Berlin, 43--60.Google Scholar
- K. Nagar and Y. N. Srikant. 2014. Precise shared cache analysis using optimal interference placement. In Proceedings of the Real-Time and Embedded Technology and Applications Symposium.Google Scholar
- K. Nagar and Y. N. Srikant. 2015b. Shared Instruction Cache Analysis in Real-Time Multi-Core Systems. Technical Report. http://www.csa.iisc.ernet.in/TR/2015/1/tech-report.pdf.Google Scholar
- Fadia Nemer, Hugues Cassé, Pascal Sainrat, Jean Paul Bahsoun, and Marianne De Michiel. 2006. PapaBench: A free real-time benchmark. In Proceedings of the Workshop on Worst-Case Execution Time Analysis (WCET’06).Google Scholar
- Marco Paolieri, Eduardo Quiñones, Franciso J. Cazorla, Guillem Bernat, and Mateo Valero. 2009. Hardware support for WCET analysis of hard real-time multicore systems. In Proceedings of the International Symposium on Computer Architecture. Google Scholar
Digital Library
- Harini Ramaprasad and Frank Mueller. 2005. Bounding worst-case data cache behavior by analytically deriving cache reference patterns. In Proceedings of the Real-Time and Embedded Technology and Applications Symposium. Google Scholar
Digital Library
- Vivy Suhendra and Tulika Mitra. 2008. Exploring locking and partitioning for predictable shared caches on multi-cores. In Proceedings of the Design Automation Conference. Google Scholar
Digital Library
- Bryan C. Ward, Jonathan L. Herman, Christopher J. Kenna, and James H. Anderson. 2013. Making shared caches more predictable on multicore platforms. In Proceedings of the Euromicro Conference on Real-Time Systems. Google Scholar
Digital Library
- Reinhard Wilhelm, Sebastian Altmeyer, Claire Burguire, Daniel Grund, Jrg Herter, Jan Reineke, Bjrn Wachter, and Stephan Wilhelm. 2010. Static timing analysis for hard real-time systems. In Verification, Model Checking, and Abstract Interpretation. Lecture Notes in Computer Science, Vol. 5944. Springer, 3--22. Google Scholar
Digital Library
- Jun Yan and Wei Zhang. 2008. WCET analysis for multi-core processors with shared L2 instruction caches. In Proceedings of the Real-Time and Embedded Technology and Applications Symposium. Google Scholar
Digital Library
- Jun Yan and Wei Zhang. 2009. Accurately estimating worst-case execution time for multi-core processors with shared direct-mapped instruction caches. In Proceedings of the International Conference on Embedded and Real-Time Computing Systems and Applications. Google Scholar
Digital Library
Index Terms
Fast and Precise Worst-Case Interference Placement for Shared Cache Analysis
Recommendations
Improving worst-case cache performance through selective bypassing and register-indexed cache
DAC '15: Proceedings of the 52nd Annual Design Automation ConferenceWorst-case execution time (WCET) analysis is a critical part of designing real-time systems that require strict timing guarantees. Data caches have traditionally been challenging to analyze in the context of WCET due to the unpredictability of memory ...
Worst-case execution time analysis-driven object cache design
Hard real-time systems need a time-predictable computing platform to enable static worst-case execution time (WCET) analysis. All performance-enhancing features need to be WCET analyzable. However, standard data caches containing heap-allocated data are ...
Stack distance based worst-case instruction cache performance analysis
SAC '11: Proceedings of the 2011 ACM Symposium on Applied ComputingThe worst-case execution time (WCET) analysis is critical to ensure the schedulability and correctness of hard real-time systems. Modern microprocessors, however, make the WCET analysis complicated, mainly because of their performance acceleration ...






Comments