Abstract
Model-based hardware design allows one to map a single model to multiple hardware and/or software architectures, essentially eliminating one of the major limitations of manual coding in C or RTL. Model-based design for hardware implementation has traditionally offered a limited set of microarchitectures, which are typically suitable only for some application scenarios. In this article we illustrate how digital signal processing (DSP) algorithms can be modeled as flexible intellectual property blocks to be used within the popular Simulink model-based design environment. These blocks are written in C and are designed for both functional simulation and hardware implementation, including architectural design space exploration and hardware implementation through high-level synthesis. A key advantage of our modeling approach is that the very same bit-accurate model is used for simulation and high-level synthesis. To prove the feasibility of our proposed approach, we modeled a fast Fourier transform (FFT) algorithm and synthesized it for different DSP applications with very different performance and cost requirements. We also implemented a high-level-synthesis (HLS) intellectual property (IP) generator that can generate flexible FFT HLS-IP blocks that can be mapped to multiple micro-/macroarchitectures, to enable design space exploration as well as being used for functional simulation in the Simulink environment.
- FFT LogiCORE - xilinx FFT IP generator. Retrieved from http://www.xilinx.com/products/intellectual- property/.Google Scholar
- FFT MegaCore function - FFT megacore® function: A high-performance, highly parameterizable FFT processor. Retrieved from http://www.altera.com/products/ip/dsp/transforms/m-ham-fft.html.Google Scholar
- LabVIEW system design software. Retrieved from http://www.ni.com/labview/.Google Scholar
- Real-time workshop: Generates C/C++ from simulink models. Retrieved from http://www.mathworks. it/products/simulink-coder/index.html.Google Scholar
- Simulink - Simulink is a block diagram environment for multidomain simulation and model-based design. Retrieved from http://www.mathworks.com/products/simulink.Google Scholar
- Simulink HDL coder - generate HDL code from simulink models and MATLAB code. Retrieved from http://www.mathworks.com/products/slhdlcoder.Google Scholar
- Synphony model compiler. Retrieved from http://www.synopsys.com/Tools/Implementation/FPGAImplementation/Pages/synphony-model-compiler.aspx.Google Scholar
- S. A. Butt and L. Lavagno. 2012a. Design space exploration and synthesis for digital signal processing algorithms from simulink models. In Proceedings of the Design and Test Symposium (IDT’12).Google Scholar
- S. A. Butt, P. Sayyah, and L. Lavagno. 2011. Model-based hardware/software synthesis for wireless sensor network applications. In Proceedings of the 2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC). 1--6. DOI:http://dx.doi.org/10.1109/SIECPC.2011.5876891Google Scholar
Cross Ref
- Shahzad Ahmad Butt and Luciano Lavagno. 2012b. Designing parameterized signal processing ips for high level synthesis in a model based design environment. In Proceedings of the 8th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS’12). ACM, New York, NY, 295--304. DOI:http://dx.doi.org/10.1145/2380445.2380493 Google Scholar
Digital Library
- Shahzad Ahmad Butt, Stéphane Mancini, Frédéric Rousseau, and Luciano Lavagno. 2014. Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework. J. Elec. Imag. 23, 5 (2014), 053012--053012.Google Scholar
Cross Ref
- V. Chouliaras, P. Galiatsatos, K. Nakos, D. Reisis, and N. Vlassopoulos. 2009. Efficient cascaded VLSI FFT architecture for OFDM systems. In Proceedings of the 16th IEEE International Conference on Electronics, Circuits, and Systems. 97--100. DOI:http://dx.doi.org/10.1109/ICECS.2009.5410928Google Scholar
- N. Dave, M. Pellauer, S. Gerding, and Arvind. 2006. 802.11a Transmitter: A case study in microarchitectural exploration. In Proceedings of the 4th ACM and IEEE International Conference on Formal Methods and Models for Co-Design. IEEE Computer Society, Washington, DC, USA, 59--68. DOI:http://dx.doi.org/ 10.1109/MEMCOD.2006.1695901 Google Scholar
Digital Library
- C. Haubelt, T. Schlichter, J. Keinert, and M. Meredith. 2008. SystemCoDesigner: Automatic design space exploration and rapid prototyping from behavioral models. In Proceedings of the 45th ACM/IEEE Design Automation Conference (DAC’08). 580--585. Google Scholar
Digital Library
- Kai Huang, Sangil Han, K. Popovici, L. Brisolara, X. Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, L. Carro, and A. A. Jerraya. 2007. Simulink-based mpsoc design flow: Case study of motion-JPEG and H.264. In Proceedings of the 2007 Design Automation Conference. 39--42. Google Scholar
Digital Library
- Hojin Kee, N. Petersen, J. Kornerup, and S. S. Bhattacharyya. 2008. Systematic generation of FPGA-based FFT implementations. In Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, 2008. 1413--1416. DOI:http://dx.doi.org/10.1109/ICASSP.2008.4517884Google Scholar
Cross Ref
- B. Kienhuis, E. Rijpkema, and E. Deprettere. 2000. Compaan: Deriving process networks from MATLAB for embedded signal processing architectures. In Proceedings of the 8th International Workshop on Hardware/Software Codesign, 2000. 13--17. Google Scholar
Digital Library
- Shuenn-Yuh Lee and Chia-Chyang Chen. 2006a. VLSI implementation of programmable FFT architectures for OFDM communication system. In Proceedings of the 2006 International Conference on Wireless Communications and Mobile Computing (IWCMC’06). ACM, New York, NY, 893--898. DOI:http://dx.doi.org/ 10.1145/1143549.1143728 Google Scholar
Digital Library
- Shuenn-Yuh Lee and Chia-Chyang Chen. 2006b. VLSI implementation of programmable FFT architectures for OFDM communication system. In Proceedings of the 2006 International Conference on Wireless Communications and Mobile Computing (IWCMC’06). ACM, New York, NY, 893--898. DOI:http://dx.doi.org/ 10.1145/1143549.1143728 Google Scholar
Digital Library
- S. Mitra. 1999. XCC-a tool for designing parameterizable IP cores in VHDL. In Proceedings of the Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers, 1999. Vol. 1. 752--756. DOI:http://dx.doi.org/ 10.1109/ACSSC.1999.832429Google Scholar
Cross Ref
- A. Molino, G. Girau, M. Nicola, M. Fantino, and M. Pini. 2008. Evaluation of a FFT-based acquisition in real time hardware and software GNSS receivers. In Proceedings of the IEEE 10th International Symposium on Spread Spectrum Techniques and Applications, 2008. 32--36. DOI:http://dx.doi.org/10.1109/ ISSSTA.2008.13Google Scholar
Cross Ref
- G. Murphy, E. M. Popovici, R. Bresnan, W. P. Marnane, and P. Fitzpatrick. 2004. Design and implementation of a parameterizable LDPC decoder IP core. In Proceedings of the 24th International Conference on Microelectronics, 2004, Vol. 2. 747--750. DOI:http://dx.doi.org/10.1109/ICMEL.2004.1314940Google Scholar
- Goran Nikolic. April 2011. Fourier Transforms—Approach to Scientific Principles. Intech Open.Google Scholar
- P. Sayyah, S. A. Butt, and L. Lavagno. 2011. Simulink-based hardware/software trade-off analysis technique. In Proceedings of the 2011 IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies (AEECT). 1--7. DOI:http://dx.doi.org/ 10.1109/AEECT.2011.6132515Google Scholar
Cross Ref
- Xiaoying Shao and Cornelis H. Slump. 2008. Quantization effects in OFDM systems. In Proceedings of the 29th Symposium on Information Theory in the Benelux. WIC organisation, Leuven, Belgium, 93--103.Google Scholar
- Andres Takach. 2010. Creating C++ IP for high performance hardware implementation of FFTs. In DesignCon2002.Google Scholar
- A. Toledo, J. Suardiaz, S. Cuenca, and A. Grediaga. 2006. Novel simulink blockset for image processing codesign. In Proceedings of the IEEE Mediterranean Electrotechnical Conference, 2006. 117--120. DOI:http://dx.doi.org/10.1109/MELCON.2006.1653050Google Scholar
- John Robert Wernsing and Greg Stitt. 2010. Elastic computing: A framework for transparent, portable, and adaptive multi-core heterogeneous computing. SIGPLAN Not. 45, 4 (April 2010), 115--124. DOI:http://dx. doi.org/10.1145/1755951.1755906 Google Scholar
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Designing Parameterizable Hardware IPs in a Model-Based Design Environment for High-Level Synthesis
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