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Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs

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Published:09 August 2016Publication History
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Abstract

In addition to optimizing for long-path timing and routability, commercial FPGA routing engines must also optimize for various timing constraints, enabling users to fine tune their designs. These timing constraints involve both long- and short-path timing requirements. The intricacies of commercial FPGA architectures add difficulty to the problem of supporting such constraints. In this work, we introduce specific delay window routing as a general method for optimization during the routing stage of the FPGA design flow, which can be applied to various timing constraints constituting both long- and short-path requirements. Furthermore, we propose a key adjustment to standard FPGA routing technology for the purposes of specific delay window routing. By using dual-wave expansion instead of traditional single-wave expansion, we solve the critical issue of inaccurate delay estimation in our wave search, which would otherwise make routing according to a specific delay window difficult. Our results show that this dual-wave method can support stricter timing constraints than the standard single-wave method. For a suite of designs with constraints requiring connections to meet a target delay within 250ps, our dual-wave method could satisfy the requirement for all designs, whereas the single-wave method failed for more than two thirds of the designs.

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  1. Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs

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      • Published in

        cover image ACM Transactions on Reconfigurable Technology and Systems
        ACM Transactions on Reconfigurable Technology and Systems  Volume 9, Issue 4
        Regular Papers and Special Section on Field Programmable Gate Arrays (FPGA) 2015
        September 2016
        161 pages
        ISSN:1936-7406
        EISSN:1936-7414
        DOI:10.1145/2984740
        • Editor:
        • Steve Wilton
        Issue’s Table of Contents

        Copyright © 2016 ACM

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 9 August 2016
        • Accepted: 1 February 2016
        • Revised: 1 December 2015
        • Received: 1 July 2015
        Published in trets Volume 9, Issue 4

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