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Fine-Grained Interconnect Synthesis

Published:11 August 2016Publication History
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Abstract

One of the key challenges for the FPGA industry going forward is to make the task of designing hardware easier. A significant portion of that design task is the creation of the interconnect pathways between functional structures. We present a synthesis tool that automates this process and focuses on the interconnect needs in the fine-grained (sub-IP-block) design space. Here there are several issues that prior research and tools do not address well: the need to have fixed, deterministic latency between communicating units (to enable high-performance local communication without the area overheads of latency insensitivity), and the ability to avoid generating unnecessary arbitration hardware when the application design can avoid it. Using a design example, our tool generates interconnect that requires 69% fewer lines of specification code than a handwritten Verilog implementation, which is a 32% overall reduction for the entire application. The resulting system, while requiring 6% more total functional and interconnect area, achieves the same performance. We also show a quantitative and qualitative advantages against an existing commercial interconnect synthesis tool, over which we achieve a 25% performance advantage and 15%/57% logic/memory area savings.

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          • Published in

            cover image ACM Transactions on Reconfigurable Technology and Systems
            ACM Transactions on Reconfigurable Technology and Systems  Volume 9, Issue 4
            Regular Papers and Special Section on Field Programmable Gate Arrays (FPGA) 2015
            September 2016
            161 pages
            ISSN:1936-7406
            EISSN:1936-7414
            DOI:10.1145/2984740
            • Editor:
            • Steve Wilton
            Issue’s Table of Contents

            Copyright © 2016 ACM

            Publisher

            Association for Computing Machinery

            New York, NY, United States

            Publication History

            • Published: 11 August 2016
            • Accepted: 1 February 2016
            • Revised: 1 December 2015
            • Received: 1 August 2015
            Published in trets Volume 9, Issue 4

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