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A Flexible SoC and Its Methodology for Parser-Based Applications

Published:24 September 2016Publication History
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Abstract

Embedded systems are being increasingly network interconnected. They are required to interact with their environment through text-based protocol messages. Parsing such messages is control dominated. The work presented in this article attempts to accelerate message parsers using a codesign-based approach. We propose a generic architecture associated with an automated design methodology that enables SoC/SoPC system generation from high-level specifications of message protocols. Experimental results obtained on a Xilinx ML605 board show acceleration factors ranging from four to 11. Both static and dynamic reconfigurations of coprocessors are discussed and then evaluated so as to reduce the system hardware complexity.

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    • Published in

      cover image ACM Transactions on Reconfigurable Technology and Systems
      ACM Transactions on Reconfigurable Technology and Systems  Volume 10, Issue 1
      March 2017
      206 pages
      ISSN:1936-7406
      EISSN:1936-7414
      DOI:10.1145/3002131
      • Editor:
      • Steve Wilton
      Issue’s Table of Contents

      Copyright © 2016 ACM

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 24 September 2016
      • Accepted: 1 May 2016
      • Revised: 1 November 2015
      • Received: 1 May 2015
      Published in trets Volume 10, Issue 1

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