skip to main content
research-article

TxRace: Efficient Data Race Detection Using Commodity Hardware Transactional Memory

Published:25 March 2016Publication History
Skip Abstract Section

Abstract

Detecting data races is important for debugging shared-memory multithreaded programs, but the high runtime overhead prevents the wide use of dynamic data race detectors. This paper presents TxRace, a new software data race detector that leverages commodity hardware transactional memory (HTM) to speed up data race detection. TxRace instruments a multithreaded program to transform synchronization-free regions into transactions, and exploits the conflict detection mechanism of HTM for lightweight data race detection at runtime. However, the limitations of the current best-effort commodity HTMs expose several challenges in using them for data race detection: (1) lack of ability to pinpoint racy instructions, (2) false positives caused by cache line granularity of conflict detection, and (3) transactional aborts for non-conflict reasons (e.g., capacity or unknown). To overcome these challenges, TxRace performs lightweight HTM-based data race detection at first, and occasionally switches to slow yet precise data race detection only for the small fraction of execution intervals in which potential races are reported by HTM. According to the experimental results, TxRace reduces the average runtime overhead of dynamic data race detection from 11.68x to 4.65x with only a small number of false negatives.

References

  1. The apache http server. http://httpd.apache.org.Google ScholarGoogle Scholar
  2. Y. Afek, A. Levy, and A. Morrison. Software-improved hardware lock elision. In Proceedings of the 2014 ACM Symposium on Principles of Distributed Computing, PODC '14, pages 212--221, 2014. ISBN 978--1--4503--2944--6.Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC Benchmark Suite: Characterization and Architectural Implications. In Proc. of the 17th PACT, Oct. 2008.Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. C. Bishop et al. Pattern recognition and machine learning. Springer New York:, 2006.Google ScholarGoogle Scholar
  5. Biswas, Zhang, Bond, and Lucia]Biswas15S. Biswas, M. Zhang, M. D. Bond, and B. Lucia. Efficient, software-only data race exceptions. In Proceedings of the 2015 ACM SIGPLAN International Conference on Object-Oriented Programming, Systems, Languages, and Applications, OOPSLA '15, 2015\natexlaba.Google ScholarGoogle Scholar
  6. Biswas, Zhang, Bond, and Lucia]Biswas15valorS. Biswas, M. Zhang, M. D. Bond, and B. Lucia. Valor: Efficient, software-only region conflict exceptions. In Proceedings of the 2015 ACM SIGPLAN International Conference on Object-Oriented Programming, Systems, Languages, and Applications, OOPSLA 2015, pages 241--259, 2015\natexlabb. ISBN 978--1--4503--3689--5.Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. J. Bobba, K. E. Moore, H. Volos, L. Yen, M. D. Hill, M. M. Swift, and D. A. Wood. Performance pathologies in hardware transactional memory. In Proceedings of the 34th Annual International Symposium on Computer Architecture, ISCA '07, pages 81--91, 2007. ISBN 978--1--59593--706--3.Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. H.-J. Boehm and S. V. Adve. Foundations of the c+ concurrency memory model. In Proceedings of the 2008 ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '08, pages 68--78, 2008.Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. M. D. Bond, K. E. Coons, and K. S. McKinley. Pacer: Proportional detection of data races. In Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '10, pages 255--268, 2010. ISBN 978--1--4503-0019--3.Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. D. Bruening, T. Garnett, and S. Amarasinghe. An infrastructure for adaptive dynamic optimization. In Proceedings of the International Symposium on Code Generation and Optimization: Feedback-directed and Runtime Optimization, CGO '03, pages 265--275, 2003. ISBN 0--7695--1913-X.Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. I. Calciu, J. Gottschlich, T. Shpeisman, G. Pokam, and M. Herlihy. Invyswell: A hybrid transactional memory for haswell's restricted transactional memory. In Proceedings of the 23rd International Conference on Parallel Architectures and Compilation, PACT '14, pages 187--200, 2014.Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. L. Chew and D. Lie. Kivati: Fast detection and prevention of atomicity violations. In Proceedings of the 5th European Conference on Computer Systems, EuroSys '10, pages 307--320, 2010. ISBN 978--1--60558--577--2.Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. J.-D. Choi, K. Lee, A. Loginov, R. O'Callahan, V. Sarkar, and M. Sridharan. Efficient and precise datarace detection for multithreaded object-oriented programs. In Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design and Implementation, PLDI '02, pages 258--269, 2002. ISBN 1--58113--463-0.Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. C. Click. Azuls experiences with hardware transactional memory. In In HP Labs - Bay Area Workshop on Transactional Memory, 2009.Google ScholarGoogle Scholar
  15. L. Dalessandro, F. Carouge, S. White, Y. Lev, M. Moir, M. L. Scott, and M. F. Spear. Hybrid norec: A case study in the effectiveness of best effort hardware transactional memory. In Proceedings of the Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XVI, pages 39--52, 2011. ISBN 978--1--4503-0266--1.Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. J. Devietti, B. P. Wood, K. Strauss, L. Ceze, D. Grossman, and S. Qadeer. Radish: Always-on sound and complete ra detection in software and hardware. In Proceedings of the 39th Annual International Symposium on Computer Architecture, ISCA '12, pages 201--212, 2012. ISBN 978--1--4503--1642--2.Google ScholarGoogle ScholarCross RefCross Ref
  17. D. Dice, Y. Lev, M. Moir, and D. Nussbaum. Early experience with a commercial hardware transactional memory implementation. In Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XIV, pages 157--168, 2009. ISBN 978--1--60558--406--5.Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. L. Effinger-Dean, B. Lucia, L. Ceze, D. Grossman, and H.-J. Boehm. Ifrit: Interference-free regions for dynamic data-race detection. In Proceedings of the ACM International Conference on Object Oriented Programming Systems Languages and Applications, OOPSLA '12, pages 467--484, 2012. ISBN 978--1--4503--1561--6.Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. T. Elmas, S. Qadeer, and S. Tasiran. Goldilocks: A race and transaction-aware java runtime. In Proceedings of the 2007 ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '07, pages 245--255, 2007. ISBN 978--1--59593--633--2.Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. J. Erickson, M. Musuvathi, S. Burckhardt, and K. Olynyk. Effective data-race detection for the kernel. In In Proceedings of the 9th USENIX conference on Operating systems design and implementation, OSDI '10, 2010.Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. C. Flanagan and S. N. Freund. Fasttrack: Efficient and precise dynamic race detection. In Proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '09, pages 121--133, 2009. ISBN 978--1--60558--392--1.Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. C. Flanagan, S. N. Freund, and J. Yi. Velodrome: A sound and complete dynamic atomicity checker for multithreaded programs. In Proceedings of the 29th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '08, pages 293--303, 2008. ISBN 978--1--59593--860--2.Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. B. Goel, R. Titos-Gil, A. Negi, S. A. McKee, and P. Stenstrom. Performance and energy analysis of the restricted transactional memory implementation on haswell. In Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, IPDPS '14, pages 615--624, Washington, DC, USA, 2014. ISBN 978--1--4799--3800--1.Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. J. L. Greathouse, Z. Ma, M. I. Frank, R. Peri, and T. Austin. Demand-driven software race detection using hardware performance counters. In Proceedings of the 38th Annual International Symposium on Computer Architecture, ISCA '11, pages 165--176, 2011. ISBN 978--1--4503-0472--6.Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. S. Gupta, F. Sultan, S. Cadambi, F. Ivancic, and M. Roetteler. Racetm: Detecting data races using transactional memory. In Proceedings of the Twentieth Annual Symposium on Parallelism in Algorithms and Architectures, SPAA '08, pages 104--106, 2008. ISBN 978--1--59593--973--9.Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. R. Haring, M. Ohmacht, T. Fox, M. Gschwind, D. Satterfield, K. Sugavanam, P. Coteus, P. Heidelberger, M. Blumrich, R. Wisniewski, a. gara, G. Chiu, P. Boyle, N. Chist, and C. Kim. The ibm blue gene/q compute chip. IEEE Micro, 32 (2): 48--60, Mar. 2012. ISSN 0272--1732.Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. W. Hasenplaugh, A. Nguyen, and N. Shavit. Quantifying the capacity limitations of hardware transactional memory. In WTTM '15: 7th Workshop on the Theory of Transactional Memory, July 2015.Google ScholarGoogle Scholar
  28. M. Herlihy and J. E. B. Moss. Transactional memory: Architectural support for lock-free data structures. In Proceedings of the 20th Annual International Symposium on Computer Architecture, ISCA '93, pages 289--300, 1993. ISBN 0--8186--3810--9.Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Intel. Intel architecture instruction set extensions programming reference. chapter 8: Intel transactional synchronization extensions, 2012. https://software.intel.com/sites/default/files/m/9/2/3/41604.Google ScholarGoogle Scholar
  30. Intel. Intel 64 and ia-32 architectures software developers manual, 2013. http://download.intel.com/products/processor/manual/325462.pdf.Google ScholarGoogle Scholar
  31. Intel. Intel 64 and ia-32 architectures optimization reference manual. chapter 12: Intel tsx recommendations, 2014. http://www.intel.com/content/dam/www/public/us/en/ documents/manuals/64-ia-32-architectures-optimization-manual.pdf.Google ScholarGoogle Scholar
  32. Intel. Intel inspector xe, 2015. http://software.intel.com/en-us/intel-inspector-xe.Google ScholarGoogle Scholar
  33. International Organization for Standardization. ISO/IEC 14882:2011: Information technology -- Programming languages -- C+, 2011.Google ScholarGoogle Scholar
  34. International Organization for Standardization. ISO/IEC 9899:2011: Information technology -- Programming languages -- C, 2011.Google ScholarGoogle Scholar
  35. C. Jacobi, T. Slegel, and D. Greiner. Transactional memory architecture and implementation for ibm system z. In Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-45, pages 25--36, 2012. ISBN 978-0--7695--4924--8.Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. C. Jung, S. Lee, E. Raman, and S. Pande. Automated memory leak detection for production use. In Proceedings of the 36th International Conference on Software Engineering, 2014.Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. B. Kasikci, C. Zamfir, and G. Candea. Racemob: Crowdsourced data race detection. In Proceedings of the Twenty-Fourth ACM Symposium on Operating Systems Principles, SOSP '13, pages 406--422, 2013. ISBN 978--1--4503--2388--8.Google ScholarGoogle ScholarDigital LibraryDigital Library
  38. K. Kelsey, T. Bai, C. Ding, and C. Zhang. Fast track: A software system for speculative program optimization. In Proceedings of the 7th Annual IEEE/ACM International Symposium on Code Generation and Optimization, CGO '09, pages 157--168, 2009. ISBN 978-0--7695--3576-0.Google ScholarGoogle ScholarDigital LibraryDigital Library
  39. C. Lattner and V. Adve. Llvm: A compilation framework for lifelong program analysis & transformation. In Proceedings of the International Symposium on Code Generation and Optimization: Feedback-directed and Runtime Optimization, CGO '04, pages 75--, 2004. ISBN 0--7695--2102--9.Google ScholarGoogle ScholarDigital LibraryDigital Library
  40. D. Lee, M. Said, S. Narayanasamy, Z. Yang, and C. Pereira. Offline symbolic analysis for multi-processor execution replay. In Proceedings of the 42Nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 42, pages 564--575, 2009. ISBN 978--1--60558--798--1.Google ScholarGoogle ScholarDigital LibraryDigital Library
  41. D. Lee, M. Said, S. Narayanasamy, and Z. Yang. Offline symbolic analysis to infer total store order. In Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture, HPCA '11, pages 357--358, 2011. ISBN 978--1--4244--9432--3.Google ScholarGoogle ScholarCross RefCross Ref
  42. D. Lee, P. M. Chen, J. Flinn, and S. Narayanasamy. Chimera: Hybrid program analysis for determinism. In Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '12, pages 463--474, 2012. ISBN 978--1--4503--1205--9.Google ScholarGoogle ScholarDigital LibraryDigital Library
  43. S. Lee, C. Jung, and S. Pande. Detecting memory leaks through introspective dynamic behavior modelling using machine learning. In Proceedings of the 36th International Conference on Software Engineering, 2014.Google ScholarGoogle ScholarDigital LibraryDigital Library
  44. Y. Lev, M. Moir, and D. Nussbaum. Ph™: Phased transactional memory. In TRANSACT '07: 2nd Workshop on Transactional Computing, aug 2007.Google ScholarGoogle Scholar
  45. Y. Liu, Y. Xia, H. Guan, B. Zang, and H. Chen. Concurrent and consistent virtual machine introspection with hardware transactional memory. In Proceedings of the 2014 IEEE 20th International Symposium on High Performance Computer Architecture, HPCA '14, 2014.Google ScholarGoogle ScholarCross RefCross Ref
  46. S. Lu, S. Park, E. Seo, and Y. Zhou. Learning from mistakes: A comprehensive study on real world concurrency bug characteristics. In Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XIII, pages 329--339, 2008. ISBN 978--1--59593--958--6.Google ScholarGoogle ScholarDigital LibraryDigital Library
  47. B. Lucia, L. Ceze, K. Strauss, S. Qadeer, and H.-J. Boehm. Conflict exceptions: Simplifying concurrent language semantics with precise hardware exceptions for data-races. In Proceedings of the 37th Annual International Symposium on Computer Architecture, ISCA '10, pages 210--221, 2010. ISBN 978--1--4503-0053--7.Google ScholarGoogle ScholarDigital LibraryDigital Library
  48. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: Building customized program analysis tools with dynamic instrumentation. In Proceedings of the 2005 ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '05, pages 190--200, 2005. ISBN 1--59593-056--6.Google ScholarGoogle ScholarDigital LibraryDigital Library
  49. J. Manson, W. Pugh, and S. V. Adve. The java memory model. In Proceedings of the 32Nd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL '05, pages 378--391, 2005. ISBN 1--58113--830-X.Google ScholarGoogle ScholarDigital LibraryDigital Library
  50. D. Marino, M. Musuvathi, and S. Narayanasamy. Literace: Effective sampling for lightweight data-race detection. In Proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '09, pages 134--143, 2009. ISBN 978--1--60558--392--1.Google ScholarGoogle ScholarDigital LibraryDigital Library
  51. M. Martin, C. Blundell, and E. Lewis. Subtleties of transactional memory atomicity semantics. IEEE Comput. Archit. Lett., 5 (2): 17--17, July 2006. ISSN 1556--6056.Google ScholarGoogle ScholarDigital LibraryDigital Library
  52. H. S. Matar, I. Kuru, S. Tasiran, and R. Dementiev. Accelerating precise race detection using commercially available hardware transactional memory support. In 5th Workshop on Determinism and Correctness in Parallel Programming, WoDet '14, 2014.Google ScholarGoogle Scholar
  53. K. E. Moore, J. Bobba, M. J. Moravan, M. D. Hill, and D. A. Wood. Log™: Log-based transactional memory. In Proceedings of the 2006 IEEE 12th International Symposium on High Performance Computer Architecture, pages 254--265, Feb. 2006.Google ScholarGoogle ScholarCross RefCross Ref
  54. z, Qi, and Torrellas]Muzahid09A. Muzahid, D. Suárez, S. Qi, and J. Torrellas. Sigrace: Signature-based data race detection. In Proceedings of the 36th Annual International Symposium on Computer Architecture, ISCA '09, pages 337--348, 2009.Google ScholarGoogle ScholarDigital LibraryDigital Library
  55. N. Nethercote and J. Seward. Valgrind: A framework for heavyweight dynamic binary instrumentation. In Proceedings of the 2007 ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '07, pages 89--100, 2007. ISBN 978--1--59593--633--2.Google ScholarGoogle ScholarDigital LibraryDigital Library
  56. R. H. B. Netzer and B. P. Miller. What are race conditions?: Some issues and formalizations. ACM Lett. Program. Lang. Syst., 1 (1): 74--88, Mar. 1992. ISSN 1057--4514.Google ScholarGoogle ScholarDigital LibraryDigital Library
  57. PCWorld. Nasdaq's facebook glitch came from race conditions, May 2012. http://www.pcworld.com/article/255911/nasdaqs_facebook_glitch_came_from_race_conditions.html.Google ScholarGoogle Scholar
  58. E. Pozniansky and A. Schuster. Multirace: Efficient on-the-fly data race detection in multithreaded c+ programs: Research articles. Concurr. Comput. : Pract. Exper., 19 (3): 327--340, Mar. 2007. ISSN 1532-0626.Google ScholarGoogle ScholarDigital LibraryDigital Library
  59. M. Prvulovic. Cord: Cost-effective (and nearly overhead-free) order-recording and data race detection. In Proceedings of the 2006 IEEE 12th International Symposium on High Performance Computer Architecture, HPCA '06, 2006.Google ScholarGoogle ScholarCross RefCross Ref
  60. M. Prvulovic and J. Torrellas. Reenact: Using thread-level speculation mechanisms to debug data races in multithreaded codes. In Proceedings of the 30th Annual International Symposium on Computer Architecture, ISCA '03, pages 110--121, 2003. ISBN 0--7695--1945--8.Google ScholarGoogle ScholarDigital LibraryDigital Library
  61. C. G. Ritson and F. R. Barnes. An evaluation of intel's restricted transactional memory for cpas, 2013.Google ScholarGoogle Scholar
  62. P. Sack, B. E. Bliss, Z. Ma, P. Petersen, and J. Torrellas. Accurate and efficient filtering for the intel thread checker race detector. In Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, ASID '06, pages 34--41, 2006. ISBN 1--59593--576--2.Google ScholarGoogle ScholarDigital LibraryDigital Library
  63. S. Savage, M. Burrows, G. Nelson, P. Sobalvarro, and T. Anderson. Eraser: A dynamic data race detector for multithreaded programs. ACM Trans. Comput. Syst., 15 (4): 391--411, Nov. 1997. ISSN 0734--2071.Google ScholarGoogle ScholarDigital LibraryDigital Library
  64. SecurityFocus. Software bug contributed to blackout, Feb. 2004. http://www.securityfocus.com/news/8016.Google ScholarGoogle Scholar
  65. K. Serebryany and T. Iskhodzhanov. Threadsanitizer: Data race detection in practice. In Proceedings of the Workshop on Binary Instrumentation and Applications, WBIA '09, pages 62--71, 2009. ISBN 978--1--60558--793--6.Google ScholarGoogle ScholarDigital LibraryDigital Library
  66. Y. Smaragdakis, J. Evans, C. Sadowski, J. Yi, and C. Flanagan. Sound predictive race detection in polynomial time. In Proceedings of the 39th Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL '12, pages 387--400, 2012. ISBN 978--1--4503--1083--3.Google ScholarGoogle ScholarDigital LibraryDigital Library
  67. M. Susskraut, T. Knauth, S. Weigert, U. Schiffel, M. Meinhold, and C. Fetzer. Prospect: A compiler framework for speculative parallelization. In Proceedings of the 8th Annual IEEE/ACM International Symposium on Code Generation and Optimization, CGO '10, pages 131--140, 2010.Google ScholarGoogle Scholar
  68. T. C. Team. Clang 3.8 threadsanitizer, 2015. http://clang.llvm.org/docs/ThreadSanitizer.html.Google ScholarGoogle Scholar
  69. J. Sevcık and D. Aspinall. On validity of program transformations in the java memory model. In Proceedings of the 22Nd European Conference on Object-Oriented Programming, ECOOP '08, pages 27--51, 2008. ISBN 978--3--540--70591--8.Google ScholarGoogle ScholarDigital LibraryDigital Library
  70. B. Wester, D. Devecsery, P. M. Chen, J. Flinn, and S. Narayanasamy. Parallelizing data race detection. In Proceedings of the Eighteenth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS '13, pages 27--38, 2013. ISBN 978--1--4503--1870--9.Google ScholarGoogle ScholarDigital LibraryDigital Library
  71. R. Wilcox. Introduction to Robust Estimation and Hypothesis Testing. Elsevier Science & Technology, 2012. ISBN 9780123869838.Google ScholarGoogle Scholar
  72. Y. Xie, M. Naik, B. Hackett, and A. Aiken. Soundness and its role in bug detection systems. In In Proceedings of the Workshop on the Evaluation of Software Defect Detection Tools, 2005.Google ScholarGoogle Scholar
  73. J. Yang, A. Cui, S. Stolfo, and S. Sethumadhavan. Concurrency attacks. In The 4th USENIX Workshop on Hot Topics in Parallelism, Berkeley, CA, 2012. USENIX. URL https://www.usenix.org/conference/ hotpar12/concurrency-attacks.Google ScholarGoogle ScholarDigital LibraryDigital Library
  74. R. M. Yoo, C. J. Hughes, K. Lai, and R. Rajwar. Performance evaluation of intel® transactional synchronization extensions for high-performance computing. In Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, SC '13, pages 19:1--19:11, 2013. ISBN 978--1--4503--2378--9.Google ScholarGoogle ScholarDigital LibraryDigital Library
  75. Y. Yu, T. Rodeheffer, and W. Chen. Racetrack: Efficient detection of data race conditions via adaptive tracking. In Proceedings of the Twentieth ACM Symposium on Operating Systems Principles, SOSP '05, pages 221--234, 2005. ISBN 1--59593-079--5.Google ScholarGoogle ScholarDigital LibraryDigital Library
  76. P. Zhou, R. Teodorescu, and Y. Zhou. Hard: Hardware-assisted lockset-based race detection. In Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, HPCA '07, pages 121--132, 2007. ISBN 1--4244-0804-0.Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. TxRace: Efficient Data Race Detection Using Commodity Hardware Transactional Memory

      Recommendations

      Comments

      Login options

      Check if you have access through your login credentials or your institution to get full access on this article.

      Sign in

      Full Access

      • Published in

        cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 51, Issue 4
        ASPLOS '16
        April 2016
        774 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/2954679
        • Editor:
        • Andy Gill
        Issue’s Table of Contents
        • cover image ACM Conferences
          ASPLOS '16: Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems
          March 2016
          824 pages
          ISBN:9781450340915
          DOI:10.1145/2872362
          • General Chair:
          • Tom Conte,
          • Program Chair:
          • Yuanyuan Zhou

        Copyright © 2016 ACM

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 25 March 2016

        Check for updates

        Qualifiers

        • research-article

      PDF Format

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader
      About Cookies On This Site

      We use cookies to ensure that we give you the best experience on our website.

      Learn more

      Got it!