Abstract
Upcoming reconfigurable Multiprocessor Systems-on-Chip (MPSoCs) present new challenges for the design and early estimation of technology requirements due to their runtime adaptive hardware architecture. The usage of simulators offers capabilities to overcome these issues. In this article, MPSoCSim, a SystemC simulator for Network-on-Chip (NoC) based MPSoCs is extended to support the simulation of reconfigurable MPSoCs. Processors, such as ARM and MicroBlaze, and peripheral models used within the virtual platform are provided by Imperas/OVP and attached to the NoC. Moreover, traffic generators are available to analyze the system. The virtual platform currently supports mesh topology with wormhole switching and several routing algorithms such as XY-, a minimal West-First algorithm, and an adaptive West-First algorithm. Amongst the impact of routing algorithms regarding performance, reconfiguration processes can be examined using the presented simulator. A mechanism for dynamic partial reconfiguration is implemented that is oriented towards the reconfiguration scheme on real FPGA platforms. It includes the simulation of the undefined behavior of the hardware region during reconfiguration and allows the adjustment of parameters. During runtime, dynamic partial reconfiguration interfaces are used to connect the Network-on-Chip infrastructure with reconfigurable regions. The configuration access ports can be modeled by the controller for the dynamic partial reconfiguration in form of an application programming interface. An additional SystemC component enables the readout of simulation time from within the application. For evaluation of the simulator timing and power consumption of the simulated hardware are estimated and compared with a real hardware implementation on a Xilinx Zynq FPGA. The comparison shows that the simulator improves the development of reconfigurable MPSoCs by early estimation of system requirements. The power estimations show a maximum deviation of 9mW at 1.9W total power consumption.
- Ankur Agarwal, Cyril Iskander, and Ravi Shankar. 2009. Survey of network on chip (NoC) architectures 8 contributions. Journal of Engineering, Computing and Architecture 3, 1.Google Scholar
- Luca Benini, Davide Bertozzi, Alessandro Bogliolo, Francesco Menichelli, and Mauro Olivieri. 2005. MPARM: Exploring the multi-processor SoC design space with SystemC. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology 41, 2 (Sept. 2005), 169--182. Google Scholar
Digital Library
- Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, and Avinoam Kolodny. 2012. HNOCS: Modular open-source simulator for heterogeneous NoCs. In Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS).Google Scholar
Cross Ref
- Alisson V. Brito, Matthias Kühnle, Michael Hübner, Jürgen Becker, and Elmar U. K. Melcher. 2007. Modelling and simulation of dynamic and partially reconfigurable systems using SystemC. In Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). Porto Alegre, Brasil. Google Scholar
Digital Library
- Paul Bourke. 1993. DFT, FFT. Retrieved from http://paulbourke.net/miscellaneous/dft/.Google Scholar
- V. Catania, A. Mineo, S. Monteleone, M. Palesi, and D. Patti. 2015. Noxim: An open, extensible and cycle-accurate network on chip simulator. In Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors.Google Scholar
- Riccardo Cattaneo, Christian Pilato, Gianluca C. Durelli, Marco D. Santambrogio, and Donatella Sciuto. 2013. SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs. In Proceedings of the 2013 International Symposium on Rapid System Prototyping (RSP).Google Scholar
Cross Ref
- J. Ceng, J. Castrillón, W. Sheng, H. Scharwächter, R. Leupers, G. Ascheid, H. Meyr, T. Isshiki, and H. Kunieda. 2008. MAPS: An integrated framework for MPSoC application parallelization. In Proceedings of the 45th ACM/IEEE Design Automation Conference (DAC). 754--759. Google Scholar
Digital Library
- Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, and Glenn Reinman. 2008. MC-Sim: An efficient simulation tool for MPSoC designs. In Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). Google Scholar
Digital Library
- Michael Dales. 2003. SWARM - SoftWare ARM. Retrieved from http://www.cl.cam.ac.uk/∼mwd24/phd/swarm.html.Google Scholar
- James J. Davis and Peter Y. K. Cheung. 2014. Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration. In Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL). 1--6.Google Scholar
- Florentine Dubois, Jose Cano, Marcello Coppola, Jose Flich, and Frederic Petro. 2011. Spidergon STNoC design flow. In Proceedings of the 5<sup>th</sup> IEEE/ACM International Symposium on Networks on Chip (NoCS). Google Scholar
Digital Library
- Liana Duenha, Marcelo Guedes, Henrique Almeida, Matheus Boy, and Rodolfo Azevedo. 2014. MPSoCBench: A toolset for MPSoC system level evaluation. In Proceedings of the 2014 International Conference on Embedded Computer Systems (ICECS).Google Scholar
Cross Ref
- M. S. Gaur, B. M. Al-Hashimi, V. Laxmi, R. Navaneeth, Naveen Choudhary, Lavina Jain, Mushtaq Ahmed, K. K. Paliwal, Varsha, Rekha, and Vineetha. 2007. NIRGAM: A simulator for NoC interconnect routing and application modeling. In Proceedings of the Workshop on Diagnostic Services in Network-on-Chips, Design, Automation and Test in Europe Conference (DATE).Google Scholar
- Diana Göhringer. 2014. Reconfigurable multiprocessor systems: Handling hydras heads -- a survey, In Proceedings of the 5th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART).Google Scholar
Digital Library
- Lingkan Gong and Oliver Diessel. 2011. ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration. In Proceedings of the 2011 International Conference on Field-Programmable Technology (FPT).Google Scholar
Cross Ref
- Kim Grüttner, Philipp A. Hartmann, Tiemo Fandrey, Kai Hylla, Daniel Lorenz, Stefan Stattelmann, Björn Sander, Oliver Bringmann, Wolfgang Nebel, and Wolfgang Rosenstiel. 2014. An ESL timing 8 power estimation and simulation framework for heterogeneous SoCs. In Proceedings of the 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation.Google Scholar
Cross Ref
- Simen Gimle Hansen, Dirk Koch, and Jim Torresen. 2013. Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDL. In Proceedings of the 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).Google Scholar
Cross Ref
- Imperas Software Limited. 2015a. OVP 8 SystemC. Retrieved from http://www.ovpworld.org/technology_systemc.Google Scholar
- Imperas Software Limited. 2015b. Using OVP Models in SystemC TLM2.0 Platforms. Retrieved from http://www.ovpworld.org/documents/OVPsim_Using_OVP_Models_in_SystemC_TLM2.0_Platforms.pdf.Google Scholar
- Imperas Software Limited. 2015c. OVPsim and Imperas CpuManager User Guide. http://www.ovpworld.org/documents/OVPsim_and_CpuManager_User_Guide.pdf.Google Scholar
- iNoCs. 2016. Homepage. Retrieved from http://www.inocs.com.Google Scholar
- L. Jain, B. Al-Hashimi, M. Gaur, V. Laxmi, and A. Narayanan. 2007. NIRGAM: A simulator for NoC interconnect routing and application modeling. In Workshop on Diagnostic Services in Network-on-Chips, Design, Automation and Test in Europe Conference (DATE). Nice, France. http://nirgam.ecs.soton.ac.uk.Google Scholar
- Nan Jiang, Daniel U. Becker, George Michelogiannakis, James Balfour, Brian Towles, John Kim, and William J. Dally. 2013. A detailed and flexible cycle-accurate network-on-chip simulator. In Proceedings of the 2013 IEEE International Symposium on Performance Analysis of Systems and Software.Google Scholar
- Muhammed Al Kadi, Patrick Rudolph, Diana Goehringer, and Michael Huebner. 2013. Dynamic and partial reconfiguration of zynq 7000 under linux. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). 1--5.Google Scholar
Cross Ref
- Leonard Masing, Stephan Werner, and Jürgen Becker. 2013. Virtual prototyping of heterogeneous dynamic platforms using open virtual platforms. In Proceedings of the 10th IEEE International Symposium on Industrial Embedded Systems (SIES).Google Scholar
- Nele Mentens, Jochen Vandorpe, J. O. Vliegen, A. N. Braeken, Bruno D. A. Silva, Abdellah Touhafi, Stephan Knappmann, Alois Kern, Jens Rettkowski, Muhammed Soubhi A. L. Kadi, Diana Göhringer, and Michael Hübner. 2015. DynamIA: Dynamic hardware reconfiguration in industrial applications. In Proceedings of the 11th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC).Google Scholar
Cross Ref
- Open Virtual Platforms -- the source of Fast Processor Models 8 Platforms. Retrieved from http://www.ovpworld.org/.Google Scholar
- Jose Renau, Basilio Fraguela, James Tuck, Wei Liu, Milos Prvulovic, Luis Ceze, Smruti Sarangi, Paul Sack, Karin Strauss, and Pablo Montesinos. 2015. SESC Simulator. Retrieved from http://sesc.sourceforge.net.Google Scholar
- Jens Rettkowski and Diana Göhringer. 2014. RAR-NoC: A reconfigurable and adaptive routable network-on-chip for FPGA-based multiprocessor systems. In Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig).Google Scholar
Cross Ref
- Felipe Rosa, Luciano Ost, Thiago Raupp, Fernando Moraes, and Ricardo Reis. 2014. Fast energy evaluation of embedded applications for many core systems. In Proceedings of the 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).Google Scholar
Cross Ref
- Stefan Schürmans, Gereon Onnebrink, Rainer Leupers, Gerd Ascheid, and Xiaotao Chen. 2015. ESL power estimation using virtual platforms with black box processor models. In Proceedings of the 3rd Workshop on Virtual Prototyping of Parallel and Embedded Systems (ViPES) as part of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XV).Google Scholar
- Synopsys, Inc. 2016. Platform Architect. Retrieved from http://www.synopsys.com/Prototyping/ArchitectureDesign/Pages/platform-architect.aspx.Google Scholar
- Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, and Axel Jantsch. 2014. Designing 2D and 3D Network-on-Chip Architectures. Springer, New York. Google Scholar
Digital Library
- Philipp Wehner, Jens Rettkowski, Tobias Kleinschmidt, and Diana Göhringer. 2015. MPSoCSim: An extended OVP simulator for modeling and evaluation of network-on-chip based heterogeneous MPSoCs. In Proceedings of the 3rd Workshop on Virtual Prototyping of Parallel and Embedded Systems (ViPES) as part of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XV).Google Scholar
- Philipp Wehner, and Diana Göhringer. 2015. Internet of things simulation using OMNeT++ and hardware in the loop. In Proceedings of the 2015 International Workshop on Components and Services for IoT Platforms: Paving the Way for IoT Standards.Google Scholar
- Stephan Werner, Leonard Masing, Fabian Lesniak, and Jürgen Becker. 2015. Software-in-the-loop simulation of embedded control applications based on virtual platforms: software-in-the-loop with open virtual platforms (OVP) using real world data and devices. In Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL).Google Scholar
- Xilinx, Inc. 2012. WP374 (v1.2): Partial Reconfiguration of Xilinx FPGAs Using ISE Design Suite. Retrieved from http://www.xilinx.com/support/documentation/white_papers/wp374_Partial_Reconfig_Xilinx_FPGAs.pdf.Google Scholar
- Xilinx, Inc. 2014. Vivado Design Suite User Guide -- Partial Reconfiguration, UG909 (v2014.4). Retrieved from http://www.xilinx.com.Google Scholar
- Xilinx, Inc. 2015a. Partial Reconfiguration in the ISE Design Suite. Retrieved from http://www.xilinx.com/tools/partial-reconfiguration.htm.Google Scholar
- Xilinx Inc. 2015b. Zynq-7000 All Programmable SoC. http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/Google Scholar
- Xilinx Inc. 2015c. Zynq-7000 All Programmable SoC -- Technical Reference Manual, UG585 (v1.10). Retrieved from http://www.xilinx.com.Google Scholar
- Xilinx Inc. 2016. PlanAhead Design and Analysis Tool. Retrieved from http://www.xilinx.com/products/design-tools/planahead.html.Google Scholar
Index Terms
Simulating Reconfigurable Multiprocessor Systems-on-Chip with MPSoCSim
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