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Source-Level Compiler Optimizations for High-Level Synthesis

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Published:25 September 2016Publication History

ABSTRACT

With high-level synthesis becoming the preferred method for hardware design, tools that operate on high-level programming languages and optimize hardware output are crucial for successful synthesis. In high-level synthesis, conventional programming language codes describe hardware behavior. Those codes are translated into RTL-level description by some appropriate tool. Common such tools that not only translate, but also optimize code, are programming language compilers. Compilers can make the transition from software to hardware smooth, allowing programmers to use their software skills on hardware programming, without any language compromises. Nonetheless, compilers also utilize optimization techniques to obtain a better output hardware description. In this paper, we discuss compiler issues for high-level synthesis, and present the results of several compiler transformations that can be implemented on our C language compiler front end of the CCC high-level synthesis tool. The results are taken from experiments conducted on the MPEG2 open-source codes, and prove the importance of such transformations in high-level synthesis.

References

  1. Banerjee, K., Karfa, C., Sarkar, D., and Mandal, C. 2014. Verification of Code Motion Techniques Using Value Propagation. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 33, No. 8, pp. 1180--1193, August 2014.Google ScholarGoogle ScholarCross RefCross Ref
  2. Cardoso, J., Diniz, P., and Weinhardt, M. 2010. Compiling for Reconfigurable Computing: A Survey. In ACM Computing Surveys, Vol. 42, No. 4, June 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Cong, J., Zhang, P., and Zou, Y. 2012. Optimizing Memory Hierarchy Allocation with Loop Transformations for High-Level Synthesis. In DAC 2012, San Francisco, California, USA, June 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Dimitriou, G., and Dossis, M. 2015. Experimenting with a High-Level Synthesis System Front End. In PACET 2015, Ioannina, May 2015; also in Journal of Engineering Science and Technology Review, 2016.Google ScholarGoogle Scholar
  5. Del Barrio, A. A., Hermida, R., Memik, S. O., Mendias, J. M., and Molina, M. C. 2012. Multispeculative Addition Applied to Datapath Synthesis. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 31, No. 12, pp. 1817--1830, December 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Dossis, M. F. 2011. A Formal Design Framework to Generate Coprocessors with Implementation Options. In International Journal of Research and Reviews in Computer Science (IJRRCS, ISSN: 2079-2557). Science Academy Publisher, United Kingdom, Vol. 2, No. 4, pp. 929--936, August 2011, DOI=http://www.sciacademypublisher.com.Google ScholarGoogle Scholar
  7. Gal, B. L., Casseau, E., and Huet, S. 2008. Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 16, No. 11, pp. 1454--1464, November 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Gupta, S., Dutt, N., Gupta, R., and Nicolau, A. 2003. Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow. Center for Embedded Computer Systems Technical Report #03-14, University of California at Irvine, April 2003.Google ScholarGoogle Scholar
  9. Gupta, S., Gupta, R. K., Dutt, N. D., and Nikolau, A. 2004. Coordinated Parallelizing Compiler Optimizations and High-Level Synthesis. In ACM Transactions on Design Automation of Electronic Systems. Vol. 9, No. 4, pp. 441--470, 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Gupta, S., Gupta, R., Dutt, N., and Nicolau, A. 2004. SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits, Kluwer Academic Publishers, 2004.Google ScholarGoogle Scholar
  11. Kountouris, A. A., and Wolinski, C. Efficient Scheduling of Conditional Behaviors for High-Level Synthesis. In ACM Transactions on Design Automation of Electronic Systems. Vol. 7, No. 3, pp. 380--412, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Morvan, A., Derrien, S., and Quinton, P. 2013. Polyhedral Bubble Insertion: A Method to Improve Nested Loop Pipelining for High-Level Synthesis. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 32, No. 3, pp. 339--352, March 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Paulin, P. G., and Knight, J. P. 1989. Force-directed scheduling for the behavioral synthesis of ASICs. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 8, No. 6, pp. 661--679, December 1989. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Plesco, A., and Risset, T. 2008. Coupling Loop Transformations and High-Level Synthesis. In RenPar'18 / SympA'2008 / CFSE'6, Fribourg, Switzerland, February 2008.Google ScholarGoogle Scholar
  15. Sarbishei, O., and Radecka, K. 2013. On the Fixed-Point Accuracy Analysis and Optimization of Polynomial Specifications. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 32, No. 6, pp. 831--844, June 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Sierra, R., Carreras, C., Caffarena, G., and López Barrio, C. A. 2015. A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 34, No. 1, pp. 52--62, January 2015.Google ScholarGoogle ScholarCross RefCross Ref
  17. Walker, R. A., and Chaudhuri, S. 1995. Introduction to the scheduling problem. In IEEE Design & Test of Computers. Vol. 12, No. 2, pp. 60--69, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Xydis, S., Palermo, G., Zaccaria, V., and Silvano, C. 2015. SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 34, No. 1, pp. 155--159, January 2015.Google ScholarGoogle ScholarCross RefCross Ref
  19. Zuo, W., Liang, Y., Li, P., Rupnow, K., Chen, D. and Cong, J. 2013. Improving High Level Synthesis Optimization Opportunity through Polyhedral Transformations, In FPGA 2013, Monterey, California, USA, February 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library

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  • Published in

    cover image ACM Other conferences
    SEEDA-CECNSM '16: Proceedings of the SouthEast European Design Automation, Computer Engineering, Computer Networks and Social Media Conference
    September 2016
    126 pages
    ISBN:9781450348102
    DOI:10.1145/2984393

    Copyright © 2016 ACM

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    Publication History

    • Published: 25 September 2016

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