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Unifying fixed code and fixed data mapping of load-imbalanced pipelined loops

Published:27 February 2016Publication History
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Abstract

Some loops with cross-iteration dependences can execute in parallel by pipelining. The loop body is partitioned into stages such that the data dependences are not violated and then the stages are mapped onto threads. Two well-known mapping techniques are fixed code and fixed data; they achieve high performance for load-balanced loops, but they fail to perform well for load-imbalanced loops. In this article, we present a novel hybrid mapping that eliminates drawbacks of both prior mapping techniques and enables dynamic scheduling of stages.

References

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  1. Unifying fixed code and fixed data mapping of load-imbalanced pipelined loops

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      • Published in

        cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 51, Issue 8
        PPoPP '16
        August 2016
        405 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/3016078
        Issue’s Table of Contents
        • cover image ACM Conferences
          PPoPP '16: Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
          February 2016
          420 pages
          ISBN:9781450340922
          DOI:10.1145/2851141

        Copyright © 2016 ACM

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 27 February 2016

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