skip to main content
research-article
Public Access

On designing NUMA-aware concurrency control for scalable transactional memory

Published:27 February 2016Publication History
Skip Abstract Section

Abstract

NUMA architectures posed the challenge of rethinking parallel applications due to the non-homogeneity introduced by their design, and their real benefits are limited to the characteristics of the particular workload. We name as partitionable transactional workloads such workloads that may be able to exploit the distributed nature of NUMA, such as transactional workloads where data and accesses can be easily partitioned among the so called NUMA zones. However, in case those workloads require the synchronization on shared data, we have to face the issue of exploiting the NUMA architecture also in the concurrency control for their transactions. Therefore in this paper we present a NUMA-aware concurrency control for transactional memory that we designed for promoting scalability in scenarios where both the transactional workload is prone to scale, and the characteristics of the underlying memory model are inherently non-uniform, such as NUMA architectures.

References

  1. J. Antony, P. P. Janes, and A. P. Rendell. Exploring Thread and Memory Placement on NUMA Architectures: Solaris and Linux, Ultra-SPARC/FirePlane and Opteron/Hypertransport. In HiPC '06, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. H. Avni and N. Shavit. Maintaining Consistent Transactional States Without a Global Clock. In SIROCCO '08, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. L. Dalessandro, M. F. Spear, and M. L. Scott. NOrec: Streamlining STM by Abolishing Ownership Records. In PPoPP '10, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. D. Dice, O. Shalev, and N. Shavit. Transactional Locking II. In DISC '06, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. D. Dice, V. J. Marathe, and N. Shavit. Lock Cohorting: A General Technique for Designing NUMA Locks. In PPoPP '12, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. A. Dragojević, R. Guerraoui, and M. Kapalka. Stretching Transactional Memory. In PLDI '09, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. P. Felber, C. Fetzer, and T. Riegel. Dynamic Performance Tuning of Word-based Software Transactional Memory. In PPoPP '08, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. T. Harris, J. Larus, and R. Rajwar. Transactional Memory, 2nd Edition. Morgan and Claypool Publishers, 2nd edition, 2010. ISBN 1608452352, 9781608452354. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. A. Israeli and L. Rappoport. Disjoint-access-parallel Implementations of Strong Shared Memory Primitives. In PODC '94, 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. JEDEC. DDR3 SDRAM standard (revision F), 2012. http://www.jedec.org/standards-documents/docs/jesd-79-3d.Google ScholarGoogle Scholar
  11. Y. Lev, V. Luchangco, V. Marathe, M. Moir, D. Nussbaum, and M. Olszewski. Anatomy of a scalable software transactional memory. In TRANSACT '09, 2009.Google ScholarGoogle Scholar
  12. N. Manchanda and K. Anand. Non-Uniform Memory Access (NUMA). New York University, 2010.Google ScholarGoogle Scholar
  13. S. Peluso, P. Romano, and F. Quaglia. SCORe: A Scalable One-copy Serializable Partial Replication Protocol. In Middleware '12, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. M. F. Spear, M. M. Michael, and C. von Praun. RingSTM: Scalable Transactions with a Single Atomic Instruction. In SPAA '08, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. TPC Council. TPC-C Benchmark, Revision 5.11. Feb. 2010.Google ScholarGoogle Scholar
  16. D. Ziakas, A. Baum, R. A. Maddox, and R. J. Safranek. Intel® Quick-Path Interconnect Architectural Features Supporting Scalable System Architectures. In HOTI '10, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. On designing NUMA-aware concurrency control for scalable transactional memory

      Recommendations

      Comments

      Login options

      Check if you have access through your login credentials or your institution to get full access on this article.

      Sign in

      Full Access

      • Published in

        cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 51, Issue 8
        PPoPP '16
        August 2016
        405 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/3016078
        Issue’s Table of Contents
        • cover image ACM Conferences
          PPoPP '16: Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
          February 2016
          420 pages
          ISBN:9781450340922
          DOI:10.1145/2851141

        Copyright © 2016 ACM

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 27 February 2016

        Check for updates

        Qualifiers

        • research-article

      PDF Format

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader
      About Cookies On This Site

      We use cookies to ensure that we give you the best experience on our website.

      Learn more

      Got it!