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Understanding and Alleviating the Impact of the Flash Address Translation on Solid State Devices

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Published:22 May 2017Publication History
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Abstract

Flash-based solid state devices (SSDs) have been widely employed in consumer and enterprise storage systems. However, the increasing SSD capacity imposes great pressure on performing efficient logical to physical address translation in a page-level flash translation layer (FTL). Existing schemes usually employ a built-in RAM to store mapping information, called mapping cache, to speed up the address translation. Since only a fraction of the mapping table can be cached due to limited cache space, a large number of extra flash accesses are required for cache management and garbage collection, degrading the performance and lifetime of an SSD. In this paper, we first apply analytical models to investigate the key factors that incur extra flash accesses during address translation. Then, we propose a novel page-level FTL with an efficient translation page-level caching mechanism, named TPFTL, to minimize the extra flash accesses. TPFTL employs a two-level least recently used (LRU) list with space-efficient optimizations to organize cached mapping entries. Inspired by the models, we further design a workload-adaptive loading policy combined with an efficient replacement policy to increase the cache hit rate and reduce the writebacks of replaced dirty entries. Finally, we evaluate TPFTL using extensive trace-driven simulations. Our evaluation results show that compared to the state-of-the-art FTLs, TPFTL significantly reduces the extra operations caused by address translation, achieving reductions on system response time and write amplification by up to 27.1% and 32.2%, respectively.

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        • Published in

          cover image ACM Transactions on Storage
          ACM Transactions on Storage  Volume 13, Issue 2
          Special Issue on MSST 2016 and Regular Papers
          May 2017
          199 pages
          ISSN:1553-3077
          EISSN:1553-3093
          DOI:10.1145/3098275
          • Editor:
          • Sam H. Noh
          Issue’s Table of Contents

          Copyright © 2017 ACM

          Publisher

          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 22 May 2017
          • Revised: 1 January 2017
          • Accepted: 1 January 2017
          • Received: 1 October 2015
          Published in tos Volume 13, Issue 2

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