Abstract
An emerging trend in safety-critical computer system design is the use of compression—for example, using cyclic redundancy check (CRC) or Fletcher checksum (FC)—to reduce the state that must be compared to verify correct redundant execution. We examine the costs and performance of CRC and FC as compression algorithms when implemented in hardware for embedded safety-critical systems. To do so, we have developed parameterizable hardware-generation tools targeting CRC and two novel FC implementations. We evaluate the resulting designs implemented for FPGA and ASIC and analyze their efficiency. While CRC is often best, FC dominates when high throughput is needed.
- A. Agrawal, G. Fohler, J. Nowotsch, S. Uhrig, and M. Paulitsch. 2016. Poster abstract: Slot-level time-triggered scheduling on COTS multicore platform with resource contentions. In 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS’16). Google Scholar
Cross Ref
- Z. Al-bayati, J. Caplan, B. H. Meyer, and H. Zeng. 2016. A four-mode model for efficient fault-tolerant mixed-criticality systems. In Design, Automation Test in Europe Conference Exhibition (DATE’16). Google Scholar
Cross Ref
- M. Baleani, A. Ferrari, L. Mangeruca, A. Sangiovanni-Vincentelli, Maurizio Peri, and Saverio Pezzini. 2003. Fault-tolerant platforms for automotive safety-critical applications. In International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES’03). 170--177.Google Scholar
Digital Library
- Robert C. Baumann. 2005. Radiation-induced soft errors in advanced semiconductor technologies. IEEE Transactions on Device Materials Reliability 5, 3, 305--316. Google Scholar
Cross Ref
- J. Caplan, M. I. Mera, P. Milder, and B. H. Meyer. 2014. Trade-offs in execution signature compression for reliable processor systems. In Design, Automation and Test in Europe Conference and Exhibition (DATE’14).Google Scholar
- Flavin Cristian. 1991. Understanding fault-tolerant distributed systems. Communications of the ACM 34, 2, 56--78. Google Scholar
Digital Library
- John G. Fletcher. 1982. An arithmetic checksum for serial transmissions. IEEE Transactions on Communications COM-30, 1, 247--252. Google Scholar
Cross Ref
- Amit Golander, Shlomo Weiss, and Ronny Ronen. 2008. DDMR: Dynamic and scalable dual modular redundancy with short validation intervals. IEEE Computer Architecture Letters 7, 2, 65--68. Google Scholar
Digital Library
- Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, and Kaushik Roy. 2011. IMPACT: Imprecise adders for low-power approximate computing. In Proceedings of the 17th IEEE/ACM International Symposium on Low-power Electronics and Design (ISLPED’11). Google Scholar
Cross Ref
- Hesham F. A. Hamed, F. A. Elmisery, and Ahmed A. H. A. Elkader. 2012. Implementation of low area and high data throughput CRC design on FPGA. International Journal of Advanced Research in Computer Science and Electronics Engineering 1, 9, 48--54.Google Scholar
- Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, and James C. Hoe. 2007. Multi-bit error tolerant caches using two-dimensional error coding. In IEEE/ACM International Symposium on Microarchitecture (MICRO). 197--209. Google Scholar
Digital Library
- J. E. Knudsen and L. T. Clark. 2006. An area and power efficient radiation hardened by design flip-flop. IEEE Transactions on Nuclear Science 53, 6, 3392--3399. Google Scholar
Cross Ref
- Philip Koopman. 2002. 32-bit cyclic redundancy codes for Internet applications. In International Conference on Dependable Systems and Networks (DSN’02). 459--468. Google Scholar
Cross Ref
- Philip Koopman. 2004. CRC Selection for Embedded Network Messages. Retrieved April 10, 2017 from https://www.ece.cmu.edu/∼koopman/crc/.Google Scholar
- Christopher LaFrieda, Engin Ipek, José F. Martinez, and Rajit Manohar. 2007. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. In International Conference on Dependable Systems and Networks (DSN’07). 317--326. Google Scholar
Digital Library
- Mojing Liu and Brett H. Meyer. 2016. Bounding error detection latency in safety critical systems with enhanced execution fingerprinting. In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS’16). Google Scholar
Cross Ref
- Theresa C. Maxino and Philip J. Koopman. 2009. The effectiveness of checksums for embedded control networks. IEEE Transactions on Dependable and Secure Computing 6, 1, 59--72. Google Scholar
Digital Library
- Albert Meixner, Micael E. Bauer, and Daniel J. Sorin. 2007. Argus: Low-cost, comprehensive error detection in simple cores. In IEEE/ACM International Symposium on Microarchitecture (MICRO’07). 210--222. Google Scholar
Digital Library
- Brett H. Meyer, Benton H. Calhoun, John Lach, and Kevin Skadron. 2011. Cost-effective safety and fault localization using distributed temporal redundancy. In International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES’11). 125--134. Google Scholar
Digital Library
- Brett H. Meyer, Mojing Liu, Jonah Caplan, and Georgi Z. Kostadinov. 2013. Rapid, tunable error detection with execution fingerprinting. In SAE 2013 AeroTech Congress and Exhibition. Google Scholar
Cross Ref
- Shubu Mukherjee. 2008. Architecture Design for Soft Errors. Morgan-Kaufmann, Burlington, MA.Google Scholar
- Victor P. Nelson. 1990. Fault-tolerant computing: Fundamental concepts. Computer 23, 7, 19--25. Google Scholar
Digital Library
- NXP. 2016. Retrieved April 10, 2017 from http://www.nxp.com/products/microcontrollers-and-processors/power-architecture-processors/qoriq-power-architecture-processors/qoriq-p4080-p4040-p4081-multicore-communications-processors:P4080.Google Scholar
- Vinod B. Prasad. 1989. Fault tolerant digital systems. IEEE Potentials 8, 1, 17--21. Google Scholar
Cross Ref
- Justin Ray and Philip Koopman. 2006. Efficient high Hamming distance CRCs for embedded networks. In International Conference on Dependable Systems and Networks (DSN’06). 3--12. Google Scholar
Digital Library
- Eric Rotenberg. 1999. AR-SMT: A microarchitectural approach to fault tolerance in microprocessors. In International Symposium on Fault-Tolerant Computing. 84--91. Google Scholar
Cross Ref
- J. Sloan, D. Kesler, R. Kumar, and A. Rahimi. 2010. A numerical optimization-based methodology for application robustification: Transforming applications for error tolerance. In IEEE/IFIP International Conference on Dependable Systems Networks (DSN’10). Google Scholar
Cross Ref
- Joseph Sloan and Rakesh Kumar. 2009. Towards scalable reliability frameworks for error prone CMPs. In International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES). 261--270. Google Scholar
Digital Library
- Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, and Andreas G. Nowatzyk. 2004. Fingerprinting: Bounding soft-error detection latency and bandwidth. In International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’04). 224--234. Google Scholar
Digital Library
- Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson. 2010. Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. In Design, Automation and Test in Europe Conference and Exhibition (DATE’10). 1572--1577. Google Scholar
Cross Ref
- Lukasz G. Szafaryn, Brett H. Meyer, and Kevin Skadron. 2013. Evaluating overheads of multibit soft-error protection in the processor core. IEEE Micro 33, 4, 56--65. Google Scholar
Digital Library
- Texas Instruments. 2016. Retrieved April 10, 2017 from http://www.ti.com/lsds/ti/microcontrollers_16-bit_32-bit/c2000_performance/safety/tms470m/overview.page.Google Scholar
- Mathys Walma. 2007. Pipelined cyclic redundancy check (CRC) calculation. In International Conference on Computer Communications and Networks. 365--370. Google Scholar
Cross Ref
Index Terms
Area, Throughput, and Power Trade-Offs for FPGA- and ASIC-Based Execution Stream Compression
Recommendations
Trade-offs in execution signature compression for reliable processor systems
DATE '14: Proceedings of the conference on Design, Automation & Test in EuropeAs semiconductor processes scale, making transistors more vulnerable to transient upset, a wide variety of microarchitectural and system-level strategies are emerging to perform efficient error detection and correction computer systems. While these ...
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors
This paper explores the area-throughput trade-off for an ASIC implementation of the Advanced Encryption Standard (AES). Different pipelined implementations of the AES algorithm as well as the design decisions and the area optimizations that lead to a ...
High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms: (Abstract Only)
FPGA '18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysData compression techniques have been widely used to reduce the data storage and movement overhead, especially in the big data era. Recent studies demonstrate the great promise of FPGAs to improve the throughput of lossless compression algorithms that ...






Comments