Noc-HMP: A Heterogeneous Multicore Processor for Embedded Systems Designed in SystemJ

Abstract

Scalability and performance in multicore processors for embedded and real-time systems usually don't go well each with the other. Networks on Chip (NoCs) provide scalable execution platforms suitable for such kind of embedded systems. This article presents a NoC-based Heterogeneous Multi-Processor system, called NoC-HMP, which is a scalable platform for embedded systems developed in the GALS language SystemJ. NoC-HMP uses a time-predictable TDMA-MIN NoC to guarantee latencies and communication time between the two types of time-predictable cores and can be customized for a specific performance goal through the execution strategy and scheduling of SystemJ program deployed across multiple cores. Examples of different execution strategies are introduced, explored and analyzed via measurements. The number of used cores can be minimized to achieve the target performance of the application. TDMA-MIN allows easy extensions of NoC-HMP with other cores or IP blocks. Experiments show a significant improvement of performance over a single core system and demonstrate how the addition of cores affects the performance of the designed system.

References

1. AICAS. 2016. JamaicaVM. Retrieved from https://www.aicas.com/cms/en/JamaicaVM.
2. Altera. 2016. Altera Cyclone V SoC. Retrieved from https://www.altera.com/products/soc/portfolio/cyclone-v-soc/overview.html.
3. C. W. Barrett, R. Sebastiani, S. A. Seshia, and C. Tinelli. 2009. Satisfiability modulo theories. Handbook of Satisfiability 185, 825--885.
4. R. Belliardi, B. Brosgol, P. Dibble, D. Holmes, and A. Wellings. 2004. The real-time specification for Java-version 1.0. 1 Java Community Process.
5. L. Benini and G. De Micheli. 2002. Networks on chips: A new SoC paradigm. Computer 35, 70--78.
6. G. Berry and G. Gonthier. 1992. The esterel synchronous programming language: Design, semantics, implementation. Science of Computer Programming 19, 87--152.
7. D. Geer. 2005. Chip makers turn to multicore processors. Computer 38, 11--13.
8. K. Goossens, J. Dielissen, and A. Radulescu. 2005. Æthereal network on chip: Concepts, architectures, and implementations. IEEE Design 8 Test of Computers 22, 414--421.
9. F. Gruian, P. Roop, Z. Salcic, and I. Radojevic. 2006. The systemJ approach to system-level design. In Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE’06. Proceedings. IEEE, 149--158.
10. C. A. R. Hoare. 1978. Communicating sequential processes. In The Origin of Concurrent Programming Springer, 413--443.
11. A. Jantsch and H. Tenhunen. 2003. Networks on Chip. Springer.
12. E. Kasapaki, M. Schoeberl, R. B. Sørensen, C. Müller, K. Goossens, and J. Sparsø. 2016. Argo: A real-time network-on-chip architecture with an efficient GALS implementation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, 479--492.
13. J. Kreuzinger, U. Brinkschulte, M. Pfeffer, S. Uhrig, and T. Ungerer. 2003. Real-time event-handling and scheduling on a multithreaded Java microcontroller. Microprocessors and Microsystems 27, 19--31.
14. C. P. Kruskal and M. Snir. 1983. The performance of multistage interconnection networks for multiprocessors. IEEE Transactions on Computers 100, 1091--1098.
15. Z. Li, A. Malik, and Z. Salcic. 2014. TACO: A scalable framework for timing analysis and code optimization of synchronous programs. In Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications. IEEE, 1--8.
16. Z. Li, A. Malik, and Z. Salcic. 2015. Reducing worst case reaction time of synchronous programs on chip-multiprocessors with application-specific TDMA scheduling. In Proceedings of the 13th International Workshop on Java Technologies for Real-time and Embedded Systems. ACM, 11.
17. Z. Li, H. Park, A. Malik, I. Kevin, K. Wang, Z. Salcic, B. Kuzmin, M. Glaß, and J. Teich. 2017. Using design space exploration for finding schedules with guaranteed reaction times of synchronous programs on multi-core architecture. Journal of Systems Architecture 74, 30--45.
18. D. Locke, B. S. Andersen, B. Brosgol, M. Fulton, T. Henties, J. J. Hunt, J. O. Nielsen, K. Nilsen, A. Ravn, M. Schoeberl, J. Vitek, and A. J. Wellings. 2017. Safety-critical Java technology specification 2017, public draft 3. Available at http://www.jcp.org/en/jsr/detail?id=302.
19. A. Malik, Z. Salcic, and P. S. Roop. 2009. SystemJ compilation using the tandem virtual machine approach. ACM Transactions on Design Automation of Electronic Systems (TODAES) 14, 34.
20. A. Malik, Z. Salcic, P. S. Roop, and A. Girault. 2010. SystemJ: A GALS language for system level design. Computer Languages, Systems 8 Structures 36, 317--344.
21. H. McGhan and M. O’Connor. 1998. Picojava: A direct execution engine for java bytecode. Computer 31, 22--30.
22. M. Nadeem, M. Biglari-Abhari, and Z. Salcic. 2012. JOP-Plus A processor for efficient execution of java programs extended with GALS concurrency. In Proceedings of the 17th Asia and South Pacific Design Automation Conference IEEE, 17--22.
23. M. Nadeem, H. Park, Z. Li, M. Biglari-Abhari, and Z. Salcic. 2013. GALS-CMP: chip-multiprocessor for GALS embedded systems. In Proceedings of the International Conference on Architecture of Computing Systems. Springer, 147--158.
24. J. D. Owens, W. J. Dally, R. Ho, D. Jayasimha, S. W. Keckler, and L.-S. Peh. 2007. Research challenges for on-chip interconnection networks. IEEE Micro 27, 96.
25. M. Paolieri, E. Quiñones, F. J. Cazorla, G. Bernat, and M. Valero. 2009. Hardware support for WCET analysis of hard real-time multicore systems. ACM SIGARCH Computer Architecture News 37, 57--68.
26. J. Parkhurst, J. Darringer, and B. Grundmann. 2006. From single core to multi-core: Preparing for a new exponential. In Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design. ACM, 67--72.
27. F. Pizlo, L. Ziarek, and J. Vitek. 2009. Real time java on resource-constrained platforms with fiji VM. In Proceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems. ACM, 1620421, 110--119.
28. E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander. 2003. Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip. IEE Proceedings-Computers and Digital Techniques 150, 294.
29. Z. Salcic and A. Malik. 2013. GALS-HMP: A heterogeneous multiprocessor for embedded applications. ACM Transactions on Embedded Computing Systems (TECS) 12, 58.
30. Z. Salcic, M. Nadeem, H. Park, and J. Teich. 2016a. A heterogeneous multi-core soc for mixed criticality industrial automation systems. In Proceedings of the 21st IEEE International Conference on Emerging Technologies and Factory Automation.
31. Z. Salcic, M. Nadeem, H. Park, and J. Teich. 2016b. Optimizing latencies and customizing noc of time-predictable heterogeneous multi-core processor. In Proceedings of the 21st IEEE International Conference on Emerging Technologies and Factory Automation.
32. Z. Salcic, M. Nadeem, and B. Striebing. 2016c. A time predictable heterogeneous multicore processor for hard real-time GALS programs. ARCS 2016.
33. M. Schoeberl. 2008. A Java processor architecture for embedded real-time systems. Journal of Systems Architecture 54, 265--286.
34. M. Schoeberl. 2012. Hardware support for embedded java. In Distributed, Embedded and Real-Time Java Systems. Springer, 159--176.
35. M. Schoeberl, S. Abbaspour, B. Akesson, N. Audsley, R. Capasso, J. Garside, K. Goossens, S. Goossens, S. Hansen, and R. Heckmann. 2015. T-CREST: Time-predictable multi-core architecture for embedded systems. Journal of Systems Architecture 61, 449--471.
36. D. Simon, C. Cifuentes, D. Cleal, J. Daniels, and D. White. 2006. Java™ on the bare metal of wireless sensor devices: The squawk java virtual machine. In Proceedings of the 2nd International Conference on Virtual Execution Environments. ACM, 78--88.
37. T. Ungerer, C. Bradatsch, M. Gerdes, F. Kluge, R. Jahr, J. Mische, J. Fernandes, P. G. Zaykov, Z. Petrov, and B. Böddeker. 2013. parMERASA - Multi-core execution of parallelised hard real-time applications supporting analysability. In Proceedings of the 2013 Euromicro Conference on Digital System Design (DSD), IEEE, 363--370.
38. T. Ungerer, F. J. Cazorla, P. Sainrat, G. Bernat, Z. Petrov, C. Rochange, E. Quinones, M. Gerdes, M. Paolieri, and J. Wolf. 2010. Merasa: Multicore execution of hard real-time applications supporting analyzability. IEEE Micro 5, 66--75.
39. Virtenio. 2016. Operating software “PreonVM” for Preon32 Series. Retrieved from http://www.virtenio.com/en/products/virtual-machine.html.
40. D. Wiklund and L. Dake. 2003. SoCBUS: switched network on chip for hard real time embedded systems. In Parallel and Distributed Processing Symposium, 2003. Proceedings. International, 8 pp.
41. W. Wolf. 2006. Design challenges in multiprocessor systems-on-chip. In From Model-Driven Design to Resource Management for Distributed Embedded Systems: IFIP TC 10 Working Conference on Distributed and Parallel Embedded Systems (DIPES 2006), B. Kleinjohann, L. Kleinjohann, R. J. Machado, C. E. Pereira, and P. S. Thiagarajan, eds. Springer, Boston, MA, 1--8.

Index Terms

• Computer systems organization

  • Architectures

    • Parallel architectures

      • Multicore architectures

  • Embedded and cyber-physical systems

    • Embedded systems